Low-power voltage regulator circuit with fast transient response, and corresponding method of operation
AssigneeSTMicroelectronics International N.V.
InventorRossella Gaudiano
Life of this patent
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AssigneeSTMicroelectronics International N.V.
InventorRossella Gaudiano
Estimating the term…
A voltage regulator has an input differential stage including a biasing current generator providing a biasing current for a biasing node, first and second input transistors coupled to the biasing node, a first cascode transistor coupled to the first input transistor at a first node, and a second cascode transistor coupled to the second input transistor at a second node. A replica transistor is between a supply node and a further node, has a gate terminal coupled to the gate terminal of an output transistor and passes a scaled-down replica current of an output current from the supply node to the further node. A current mirror coupled to the replica transistor senses the scaled-down replica current, sinks a first additional biasing current based on the scaled-down replica current from the first node, and sinks a second additional biasing current based on the scaled-down replica current from the second node.
A voltage regulator circuit, comprising:
A method of operating a voltage regulator circuit comprising an input differential stage having a biasing current generator, an input differential pair of transistors comprising a first input transistor and a second input transistor, both coupled to a biasing node of the biasing current generator, and a pair of cascode transistors comprising a first cascode transistor coupled to the first input transistor at a first node, and a second cascode transistor coupled to the second input transistor at a second node, the voltage regulator circuit further comprising an output stage comprising an output transistor having a conductive channel disposed between a supply node and an output node of the voltage regulator circuit, a replica transistor having a conductive channel between the supply node and a further node, and a gate terminal coupled to the gate terminal of the output transistor, and a current mirror coupled to the replica transistor, the method comprising:
Dependencies are inferred from the claim text.