Semiconductor testing structure

Abstract

A semiconductor test structure includes a carrier; a conductive layer disposed on the carrier and including a continuous surface with a first region and a second region; a first adhesive portion and a second adhesive portion disposed on the conductive layer in a configuration of covering the first region and exposing the second region; and a first semiconductor device and a second semiconductor device disposed on the first adhesive portion and the second adhesive portion, respectively, wherein the first semiconductor device includes a first lower electrode, a first semiconductor stack, and a first upper electrode, in a cross-sectional view, the first lower electrode faces the first adhesive portion, the first upper electrode faces away from the first adhesive portion.

Dependencies are inferred from the claim text.