Semiconductor devices including insulating structure

A semiconductor device comprising:

• a semiconductor substrate including a device region, a buffer region surrounding the device region, and an edge region surrounding the buffer region;
• an interconnection structure disposed on the semiconductor substrate and including a plurality of interconnection pattern layers, the interconnection structure having a side surface defined between the buffer region and the edge region;
• a first insulating structure on the interconnection structure, including
• a first insulating portion including a portion extending in a first direction along an upper surface of the interconnection structure, in the device region, the buffer region, and the edge region, and
• a second insulating portion extending downwardly from the first insulating portion and covering the side surface of the interconnection structure, in the edge region;
• a lower conductive pattern on the first insulating structure;
• a second insulating structure on the lower conductive pattern;
• a first conductive via penetrating the first insulating structure and connecting at least a portion of the plurality of interconnection pattern layers and the lower conductive pattern;
• an upper conductive pattern on the second insulating structure;
• and
• a second conductive via penetrating the second insulating structure and connecting the lower conductive pattern and the upper conductive pattern.

A semiconductor device comprising:

• a lower structure;
• and
• an upper structure on the lower structure,
• wherein the lower structure includes,
• a semiconductor substrate including a device region, a buffer region surrounding the device region, and an edge region surrounding the buffer region;
• a device layer on the semiconductor substrate;
• an interconnection structure disposed on the device layer and including a plurality of interconnection pattern layers and an insulating layer covering the plurality of interconnection pattern layers, the interconnection structure having a side surface defined between the buffer region and the edge region;
• a first insulating structure on the interconnection structure;
• a lower conductive pattern disposed on the first insulating structure;
• and
• a second insulating structure on the lower conductive pattern,
• wherein the upper structure includes,
• an upper conductive pattern on the second insulating structure;
• and
• a passivation structure covering the upper conductive pattern, on the second insulating structure, and having an opening exposing at least a portion of the upper conductive pattern,
• wherein the first insulating structure includes,
• a first insulating portion including a portion disposed above the interconnection structure, in the device region and the buffer region;
• and
• a second insulating portion extending downwardly from at least a portion of the first insulating portion and covering the side surface of the interconnection structure, a lower end of the second insulating portion extending into the device layer, and
• wherein at least a portion of a side surface of the lower structure is defined by a side surface of the first insulating structure and a side surface of the second insulating structure aligned with each other.