Transistor gate runner topology
AssigneeSemiconductor Components Industries, LLC
InventorRoman MALOUSEK
Life of this patent
Estimating the term…
Abstract
A transistor is disclosed. The transistor includes a termination region extending around an exterior of a semiconductor die, a transition region located interior to the termination region, a first active region located interior to the transition region along at least a first edge of the semiconductor die, and a second active region above which a source pad area is included. The transistor further includes a gate runner including at least a first side portion located between the first active region and the second active region and extending parallel to the first edge of the semiconductor die.
Claims20
A transistor comprising:
- a termination region extending around an exterior of a semiconductor die;
- a transition region located interior to the termination region;
- a first active region located interior to the transition region along at least a first edge of the semiconductor die;
- a second active region above which a source pad area is included;
- and
- a gate runner including at least a first side portion located between the first active region and the second active region and extending parallel to the first edge of the semiconductor die.
A transistor comprising:
- a termination region extending around an exterior of a semiconductor die;
- a transition region located interior to the termination region;
- a first active region located interior to the transition region along at least a first edge of the semiconductor die;
- a second active region above which multiple source pad areas are included;
- a third active region located interior to the transition region along at least a second edge of the semiconductor die that opposes the first edge of the semiconductor die;
- and
- a gate runner including:
- a first side portion located between the first active region and the second active region and extending parallel to the first edge of the semiconductor die;
- a second side portion located between the third active region and the second active region and extending parallel to the second edge of the semiconductor die;
- a cross-bar extending from the first side portion to the second side portion;
- and
- a central portion extending from the cross-bar and parallel to a length of the first side portion and the second side portion.
A method for forming a transistor, comprising:
- forming a termination region extending around an exterior of a semiconductor die;
- forming a transition region located interior to the termination region;
- forming a first active region located interior to the transition region along at least a first edge of the semiconductor die;
- forming a second active region above which a first source pad area is to be included;
- and
- forming a gate runner including at least a first side portion located between the first active region and the second active region and extending parallel to the first edge of the semiconductor die.
Dependencies are inferred from the claim text.