Barrier-free approach for forming contact plugs
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChing-Yi Chen, Sheng-Hsuan Lin, Wei-Yip Loh, Hung-Hsu Chen, Chih-Wei Chang
Life of this patent
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Abstract
A method includes etching a dielectric layer of a substrate to form an opening in the dielectric layer, forming a metal layer extending into the opening, performing an anneal process, so that a bottom portion of the metal layer reacts with a semiconductor region underlying the metal layer to form a source/drain region, performing a plasma treatment process on the substrate using a process gas including hydrogen gas and a nitrogen-containing gas to form a silicon-and-nitrogen-containing layer, and depositing a metallic material on the silicon-and-nitrogen-containing layer.
Claims21
(canceled)
An integrated circuit structure comprising:
- a semiconductor region;
- a gate stack over the semiconductor region;
- a dielectric gate cap over the gate stack;
- an etch stop layer over and interfacing the dielectric gate cap;
- a source/drain region on a side of the gate stack;
- a source/drain silicide region over and contacting the source/drain region;
- a silicon nitride layer over the source/drain silicide region;
- and
- a contact plug comprising portions on opposing sides of the silicon nitride layer, wherein the silicon nitride layer interfaces with sidewalls of the contact plug, and wherein the contact plug is joined to the etch stop layer.
An integrated circuit structure comprising:
- a source/drain region;
- a source/drain silicide layer over and joined to the source/drain region;
- a plurality of dielectric layers over the source/drain region;
- an etch stop layer over the plurality of dielectric layers;
- an additional dielectric layer over the etch stop layer;
- a silicon nitride layer comprising:
- a sidewall portion interfacing with sidewalls of the plurality of dielectric layers;
- and
- a bottom portion;
- a metallic region in the silicon nitride layer and in contact with the silicon nitride layer;
- and
- a gate spacer, wherein the silicon nitride layer is between the gate spacer and the metallic region, and the silicon nitride layer is spaced apart from the gate spacer.
An integrated circuit structure comprising:
- a gate stack comprising:
- a gate dielectric;
- and
- a gate electrode over the gate dielectric;
- a dielectric gate cap over and contacting the gate dielectric and the gate electrode;
- a first source/drain region;
- a first source/drain silicide layer over and electrically coupled to the first source/drain region;
- a first contact plug over and electrically coupled to the first source/drain silicide layer;
- a silicon nitride layer comprising a sidewall portion contacting the first contact plug, wherein the sidewall portion of the silicon nitride layer contacts the first contact plug;
- a contact etch stop layer over the first source/drain region;
- and
- an inter-layer dielectric over the contact etch stop layer, wherein the silicon nitride layer is between the inter-layer dielectric and the first contact plug.
Dependencies are inferred from the claim text.