Semiconductor device interconnect layer formation by selective ion implantation
AssigneeAxcelis Technologies, Inc.
InventorAnthony Lee
Life of this patent
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Abstract
A method for forming an interconnect layer for a semiconductor device includes depositing a first conductive layer on a semiconductor wafer, the first conductive layer having a thickness less than a desired final thickness of the interconnect layer; implanting an implant species into a top surface of the first conductive layer, wherein the implant species is selected so as to mitigate a stress developed in the first layer; and depositing one or more additional conductive layers upon the implanted first conductive layer up to the desired final thickness of the interconnect layer.
Claims18
A method for forming an interconnect layer for a semiconductor device, the method comprising:
- depositing a first conductive layer on a semiconductor wafer, the first conductive layer having a thickness less than a desired final thickness of the interconnect layer;
- implanting an implant species into a top surface of the first conductive layer, wherein the implant species is selected so as to mitigate a stress developed in the first layer;
- and
- depositing one or more additional conductive layers upon the implanted first conductive layer up to the desired final thickness of the interconnect layer.
A combination ion implantation and deposition system, the system comprising:
- a process chamber;
- an ion source configured to generate a desired ion species for implantation;
- a beamline module configured to transport the desired ion species to the process chamber, wherein the process chamber further comprises a secondary chamber having a material deposition source therein;
- and
- a controller configured to:
- deposit, using the material deposition source, a first conductive layer on a semiconductor wafer disposed within the process chamber, the first conductive layer having a thickness less than a desired final thickness of an interconnect layer of a semiconductor device formed on the semiconductor wafer;
- implant the desired implant species into a top surface of the first conductive layer, wherein the implant species is selected so as to mitigate a stress developed in the first layer;
- and
- deposit, using the material deposition source, one or more additional conductive layers upon the implanted first conductive layer up to the desired final thickness of the interconnect layer.
Dependencies are inferred from the claim text.