Transistor having an independently controlled body contact region which has a reduced length to reduce parasitic capacitance

A method for fabricating an electronic device to reduce parasitic capacitance, comprising:

• fabricating an insulation layer extending in a first direction and a second direction orthogonal to the first direction;
• and
• fabricating a semiconductor layer extending in the first direction and the second direction, the semiconductor layer adjacent to the insulation layer in a third direction orthogonal to the first direction and the second direction, wherein fabricating the semiconductor layer comprises:
• fabricating a body region;
• fabricating a drain region of a first polarity and adjacent to a first side of the body region in the first direction, the drain region extending in the second direction;
• and
• fabricating a source region of the first polarity and adjacent to a second side of the body region opposite the first side in the first direction, the source region extending in the second direction;
• fabricating a poly region, comprising:
• fabricating a gate region extending in the first direction and the second direction, the gate region adjacent to the body region in the third direction, the body region between the drain region and the source region, the gate region having a gate length extending in the first direction and a gate width extending in the second direction from a first gate end to a second gate end;
• and
• fabricating a poly extension region extending in the second direction from the first gate end;
• fabricating a body contact region having a second polarity and directly adjacent, in the second direction, to a third side of the body region, and under the poly extension region, wherein the body contact region has a body contact region length in the first direction equal to the gate length;
• and
• fabricating a body contact coupled to the body contact region independent of the source region.

An n-type field-effect transistor (FET) (NFET), comprising:

• a semiconductor layer extending in a first direction and a second direction orthogonal to the first direction, the semiconductor layer comprising:
• a body region;
• an n-type drain region adjacent to a first side of the body region in the first direction, the n-type drain region extending in the second direction;
• an n-type source region adjacent to a second side of the body region opposite the first side in the first direction, the n-type source region extending in the second direction;
• a poly region, comprising:
• a gate region extending in the first direction and the second direction, the gate region above the body region, the body region between the n-type drain region and the n-type source region, the gate region having a gate length extending in the first direction and a gate width extending in the second direction from a first gate end to a second gate end;
• and
• a poly extension region extending in the second direction from the first gate end;
• a p-type body contact region directly adjacent, in the second direction, to a third side of the body region, and under the poly extension region, wherein the p-type body contact region has a body contact region length in the first direction equal to the gate length;
• and
• a body contact coupled to the p-type body contact region independent of the n-type source region.