Semiconductor device with front via
AssigneeInternational Business Machines Corporation
InventorsAnindya Nath, Robert Gauthier, Masoud Zabihi, Anthony I-Chih Chou
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a first well region, a second well region adjacent to the first well region, a plurality of doped regions over the first well region and the second well region, a first backside via on a first end of the semiconductor device, a second backside via on a second end of the semiconductor device, a first deep via connecting the first backside via to a frontside contact, a second deep via over the second backside via, and shallow trench isolation (STI) covering the first deep via and the second deep via. The first backside via and the second backside via are covered by a spacer liner.
Claims20
A semiconductor device, comprising:
- a first well region;
- a second well region adjacent to the first well region;
- one or more doped regions over each of the first well region and the second well region;
- a first backside via on a first side of the semiconductor device;
- a second backside via on a second side of the semiconductor device, wherein the first side is located on an opposite side of the second side;
- a first deep via connecting the first backside via to a frontside contact;
- a second deep via over the second backside via;
- and
- shallow trench isolation (STI) covering the first deep via and the second deep via,
- wherein the first backside via and the second backside via are covered by a spacer liner.
A method for fabrication of a semiconductor device, the method comprising:
- forming a first well region;
- forming a second well region adjacent to the first well region;
- forming one or more doped regions over each of the first well region and the second well region;
- forming a first backside via on a first end of the semiconductor device;
- forming a second backside via on a second end of the semiconductor device;
- forming a first deep via connecting the first backside via to a frontside contact;
- forming a second deep via over the second backside via;
- covering the first deep via and the second deep via by shallow trench isolation (STI);
- and
- covering the first backside via and the second backside via by a spacer liner.
A semiconductor device, comprising:
- a well region;
- a plurality of doped regions over the well region;
- a backside via on a first end of the semiconductor device;
- a deep via connecting the backside via to a frontside contact;
- and
- shallow trench isolation (STI) covering the deep via,
- wherein:
- a gate region extends over the well region, and
- the gate region has no doped region adjacent to it on a drain side.
Dependencies are inferred from the claim text.