Semiconductor device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorShunpei YAMAZAKI
Life of this patent
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Abstract
Disclosed is a semiconductor device capable of functioning as a memory device. The memory device comprises a plurality of memory cells, and each of the memory cells contains a first transistor and a second transistor. The first transistor is provided over a substrate containing a semiconductor material and has a channel formation region in the substrate. The second transistor has an oxide semiconductor layer. The gate electrode of the first transistor and one of the source and drain electrodes of the second transistor are electrically connected to each other. The extremely low off current of the second transistor allows the data stored in the memory cell to be retained for a significantly long time even in the absence of supply of electric power.
Claims27
(canceled)
A semiconductor device comprising:
- a first transistor including a first channel formation region;
- a second transistor including a second channel formation region;
- a first conductive film configured to be a gate of the first transistor;
- a first insulating film provided over the first conductive film;
- a second conductive film provided over the first insulating film, and configured to be a gate of the second transistor;
- a second insulating film provided over the second conductive film, and configured to be a gate insulating film of the second transistor;
- an oxide semiconductor film provided over the second insulating film, and including the second channel formation region;
- and
- a third insulating film provided over the oxide semiconductor film,
- wherein the first channel formation region includes silicon,
- wherein one of a source and a drain of the second transistor is electrically connected to the gate of the first transistor, and
- wherein in plan view, the first conductive film does not overlap the second channel formation region.
A semiconductor device comprising:
- a first transistor including a first channel formation region;
- a second transistor including a second channel formation region;
- a first conductive film configured to be a gate of the first transistor;
- a first insulating film provided over the first conductive film;
- a second conductive film provided over the first insulating film, and configured to be a gate of the second transistor;
- a second insulating film provided over the second conductive film, and configured to be a gate insulating film of the second transistor;
- an oxide semiconductor film provided over the second insulating film, and including the second channel formation region;
- and
- a third insulating film provided over the oxide semiconductor film,
- wherein the first channel formation region includes silicon,
- wherein one of a source and a drain of the second transistor is electrically connected to the gate of the first transistor,
- wherein in plan view, the first conductive film does not overlap the second channel formation region,
- wherein the second insulating film has a region in contact with the oxide semiconductor film, and includes silicon and oxygen, and
- wherein the third insulating film has a region in contact with the oxide semiconductor film, and includes silicon and oxygen.
A semiconductor device comprising:
- a first transistor including a first channel formation region;
- a second transistor including a second channel formation region;
- a first conductive film configured to be a gate of the first transistor;
- a first insulating film provided over the first conductive film;
- a second conductive film provided over the first insulating film, and configured to be a gate of the second transistor;
- a second insulating film provided over the second conductive film, and configured to be a gate insulating film of the second transistor;
- an oxide semiconductor film provided over the second insulating film, and including the second channel formation region;
- a third insulating film provided over the oxide semiconductor film;
- and
- a third conductive film provided over the third insulating film,
- wherein the first channel formation region includes silicon,
- wherein one of a source and a drain of the second transistor is electrically connected to the gate of the first transistor,
- wherein in plan view, the first conductive film does not overlap the second channel formation region,
- wherein the first conductive film is electrically connected to the oxide semiconductor film through the third conductive film,
- wherein in plan view, a maximum length of the oxide semiconductor film in a channel length direction of the second transistor is larger than a maximum length of the oxide semiconductor film in a channel width direction of the second transistor,
- wherein in plan view, a maximum length of the third conductive film in the channel length direction of the second transistor is larger than a maximum length of the third conductive film in the channel width direction of the second transistor,
- wherein in plan view, a maximum length of the first conductive film in the channel width direction of the second transistor is larger than a maximum length of a region where the third conductive film overlaps the first conductive film in the channel width direction of the second transistor, and
- wherein in plan view, a maximum length of the first conductive film in the channel width direction of the second transistor is larger than a maximum length of the oxide semiconductor film in the channel width direction of the second transistor.
A semiconductor device comprising:
- a first transistor including a first channel formation region;
- a second transistor including a second channel formation region;
- a first conductive film configured to be a gate of the first transistor;
- a first insulating film provided over the first conductive film;
- a second conductive film provided over the first insulating film, and configured to be a gate of the second transistor;
- a second insulating film provided over the second conductive film, and configured to be a gate insulating film of the second transistor;
- an oxide semiconductor film provided over the second insulating film, and including the second channel formation region;
- a third insulating film provided over the oxide semiconductor film;
- and
- a third conductive film provided over the third insulating film,
- wherein the first channel formation region includes silicon,
- wherein one of a source and a drain of the second transistor is electrically connected to the gate of the first transistor,
- wherein in plan view, the first conductive film does not overlap the second channel formation region,
- wherein the first conductive film is electrically connected to the oxide semiconductor film through the third conductive film,
- wherein in plan view, a maximum length of the oxide semiconductor film in a channel length direction of the second transistor is larger than a maximum length of the oxide semiconductor film in a channel width direction of the second transistor,
- wherein in plan view, a maximum length of the third conductive film in the channel length direction of the second transistor is larger than a maximum length of the third conductive film in the channel width direction of the second transistor,
- wherein in plan view, a maximum length of the first conductive film in the channel width direction of the second transistor is larger than a maximum length of a region where the third conductive film overlaps the first conductive film in the channel width direction of the second transistor,
- wherein in plan view, a maximum length of the first conductive film in the channel width direction of the second transistor is larger than a maximum length of the oxide semiconductor film in the channel width direction of the second transistor,
- wherein the second insulating film has a region in contact with the oxide semiconductor film, and includes silicon and oxygen, and
- wherein the third insulating film has a region in contact with the oxide semiconductor film, and includes silicon and oxygen.
Dependencies are inferred from the claim text.