Maintaining a virtual time of day
AssigneeSkyworks Solutions, Inc.
InventorVivek Sarda
Life of this patent
Estimating the term…
Abstract
Time of day (ToD) registers provide respective virtual ToDs corresponding to the occurrence of edges of input clock signals being supplied to an integrated circuit. The integrated circuit generates a heartbeat clock signal having a frequency higher than a SYNC signal and time stamps the heartbeat clock signal to generate heartbeat time stamps. The heartbeat time stamps are used along with the time stamps of the input clock signals to determine the time of day corresponding to occurrences of edges of the input clock signals.
Claims21
(canceled)
A method for providing time of day values in a network timing system, the method comprising, with circuitry of a first timing card of the network timing system:
- based on timestamping of a synchronization signal, generating a conversion factor for converting from an internal time domain to a network time domain;
- generating a clock signal having a frequency higher than a frequency of the synchronization signal;
- and
- based on timestamping of the clock signal, timestamping of an input signal, and the conversion factor, generating a time of day of an edge of the input signal.
A network line card comprising:
- first circuitry configured to, based on timestamping of a synchronization signal, generate a conversion factor for converting from an internal time domain to a network time domain;
- and
- second circuitry configured to generate a first time of day corresponding to an edge of an input signal in a network time domain, the first time of day being generated by the second circuitry based on:
- timestamping of an internal clock, timestamping of the input signal, and the conversion factor.
A network timing system comprising:
- a slave line card;
- a plurality of master line cards;
- and
- a master timing card communicatively coupled to supply a clock signal to the slave line card and the plurality of master line cards, the master timing card including first circuitry configured to, based on timestamping of a synchronization signal, generate a conversion factor for converting from an internal time domain to a network time domain, and the master timing card further including second circuitry configured to generate a first time of day corresponding to an edge of an input signal in a network time domain, the first time of day being generated by the second circuitry based on:
- timestamping of an internal clock, timestamping of the input signal, and the conversion factor.
Dependencies are inferred from the claim text.