Encoder, Encoding Method, and Chip

An encoding method, wherein the method is applied to an encoder, and wherein the method comprises:

• receiving, by a first feedforward circuit of the encoder and per cycle, n first symbols of to-be-encoded data in parallel, wherein n is a positive integer;
• performing, by the first feedforward circuit and based on the n first symbols received in a current cycle, calculation in a finite field to obtain a single-cycle polynomial corresponding to the current cycle, wherein the single-cycle polynomial indicates the n first symbols received by the first feedforward circuit in the current cycle;
• receiving, by a first feedback circuit of the encoder and from the first feedforward circuit, the single-cycle polynomial;
• and
• performing, by the first feedback circuit and based on the single-cycle polynomial and a first polynomial indicating a second symbol received in a historical cycle, calculation in the finite field to obtain a second polynomial,
• wherein the second polynomial indicates third symbols received from an initial cycle to the current cycle,
• wherein the second polynomial is configured to determine a first target polynomial indicating the to-be-encoded data,
• wherein the first target polynomial is configured to generate a check sequence of the to-be-encoded data,
• wherein the check sequence is configured to check and correct the to-be-encoded data,
• wherein a codeword from encoding, based on a forward error correction encoding scheme, the to-be-encoded data comprises the to-be-encoded data and the check sequence,
• wherein the initial cycle is a first cycle for the first feedforward circuit to receive the to-be-encoded data, and
• wherein the historical cycle is located before the current cycle in a process in which the first feedforward circuit receives the to-be-encoded data.

A chip, comprising:

• an encoding circuit configured to encode, based on a forward error correction encoding scheme, to-be-encoded data by:
• receiving, per cycle, n first symbols of to-be-encoded data in parallel, wherein n is a positive integer;
• performing, based on the n first symbols received in a current cycle, calculation in a finite field to obtain a single-cycle polynomial corresponding to the current cycle, wherein the single-cycle polynomial indicates the n first symbols received by a first feedforward circuit of the encoding circuit in the current cycle;
• receiving, from the first feedforward circuit, the single-cycle polynomial;
• and
• performing, based on the single-cycle polynomial and a first polynomial indicating a second symbol received in a historical cycle, calculation in the finite field to obtain a second polynomial,
• wherein the second polynomial indicates third symbols received from an initial cycle to the current cycle,
• wherein the second polynomial is configured to determine a first target polynomial indicating the to-be-encoded data,
• wherein the first target polynomial is configured to generate a check sequence of the to-be-encoded data,
• wherein the check sequence is configured to check and correct the to-be-encoded data,
• wherein a codeword from encoding, based on the forward error correction encoding scheme, the to-be-encoded data comprises the to-be-encoded data and the check sequence,
• wherein the initial cycle is a first cycle for the first feedforward circuit to receive the to-be-encoded data, and
• wherein the historical cycle is located before the current cycle in a process in which the first feedforward circuit receives the to-be-encoded data.