Bootstrapped switch circuit with high linearity

A sample circuit, comprising:

• a signal generator configured to generate a sample signal, a hold signal, and a tracking signal;
• and
• a bootstrapped switch circuit comprising:
• a sample transistor comprising a gate, a source coupled to an input terminal and a drain coupled to an output terminal of the bootstrapped switch circuit;
• a bootstrap capacitor;
• a charge path configured to charge the bootstrap capacitor during a hold phase;
• a bootstrap path configured to apply a voltage of the bootstrap capacitor to the gate of the sample transistor during a sample phase, the bootstrap path including:
• a low-side transistor configured to couple a first terminal of the bootstrap capacitor to the source of the sample transistor during the sample phase;
• and
• a high-side transistor configured to couple a second terminal of the bootstrap capacitor to the gate of the sample transistor during the sample phase;
• and
• a bootstrap transistor having gate coupled to the gate of the sample transistor and a drain coupled to a gate of the high-side transistor, the bootstrap transistor configured to maintain an on-state of the high-side transistor during the sample phase after the high-side transistor is initially turned on during the sample phase;
• and
• a high-side drive circuit including:
• a first high-side drive transistor coupled between a high power supply terminal and the gate of the high-side transistor;
• and
• a second high-side drive transistor coupled between the gate of the high-side transistor the first terminal of the bootstrap capacitor;
• and
• wherein a gate of the first high-side drive transistor is driven by the sample signal to drive the first high-side drive transistor in an off-state during the sample phase and in an on-state during the hold phase;
• and
• wherein a gate of the second high-side drive transistor is driven by the tracking signal to drive the second high-side drive transistor in an on-state during an initial portion of the sample phase and to drive the second high-side drive transistor in an off-state during a remaining portion of the sample phase and further during the hold phase.

A analog-to-digital converter (ADC), comprising:

• a bootstrapped switch circuit including:
• a sample transistor comprising a gate, a source coupled to an input terminal, and a drain coupled to an output terminal of the bootstrapped switch circuit;
• a bootstrap capacitor;
• a charge path configured to charge the bootstrap capacitor during a hold phase;
• and
• a bootstrap path configured to apply a voltage of the bootstrap capacitor to the gate of the sample transistor during a sample phase, the bootstrap path including:
• a low-side transistor configured to couple a first terminal of the bootstrap capacitor to the source of the sample transistor during the sample phase;
• and
• a high-side transistor configured to couple a second terminal of the bootstrap capacitor to the gate of the sample transistor during the sample phase;
• a bootstrap transistor having gate coupled to the gate of the sample transistor and a drain coupled to a gate of the high-side transistor, the bootstrap transistor configured to maintain an on-state of the high-side transistor during the sample phase after the high-side transistor is initially turned on during the sample phase;
• a capacitive digital-to-analog converter (DAC) configured to receive an input signal via the bootstrapped switch circuit during the sample phase and to receive a digital feedback signal during the hold phase;
• a comparator coupled to the DAC and configured to generate a comparison signal based on a DAC output;
• and
• a successive-approximation register (SAR) logic coupled to receive the comparison signal and to provide the digital feedback signal to the capacitive DAC.