Fast-settling threshold estimator for a bit slicer

An electronic circuit for determining a slicing level of digital data in an analog signal, comprising:

• a bit-slicing voltage comparator having a positive input terminal for receiving an analog signal containing digital data, a negative input terminal, and an output terminal for outputting a binary signal based on the digital data;
• a fast-settling threshold estimator for producing a fast-settling threshold voltage, the fast-settling threshold estimator having an input terminal for receiving the analog signal and an output terminal coupled to the negative input terminal of the bit-slicing voltage comparator, wherein the fast-settling threshold estimator includes:
• a maximum peak detector having an input terminal for receiving the analog signal and having an output terminal, wherein the maximum peak detector produces at its output terminal an estimate of a maximum value of the analog signal,
• a differentiator having an input terminal coupled to the output terminal of the maximum peak detector, and having an output terminal, wherein the differentiator produces an output signal responsive to a change in the analog signal,
• a second comparator having a first input terminal coupled to the differentiator and a second input terminal coupled to a constant voltage source having a preselected voltage and having an output terminal, wherein the second comparator outputs a pulse when a voltage of the output signal of the differentiator is greater than the preselected voltage, and
• a minimum peak detector having a first input terminal for receiving the analog signal and a reset input terminal for receiving the pulse, wherein the pulse resets the minimum peak detector and, after being reset, the minimum peak detector outputs at an output terminal an estimate of a minimum value of the analog signal;
• and
• an averaging circuit coupled to the maximum peak detector and to the minimum peak detector for producing a weighted average of the estimate of a maximum value of the analog signal and the estimate of a minimum value of the analog signal, wherein the weighted average is a fast-settling threshold voltage of a slicing level of the digital data.

A radio frequency (RF) receiver, comprising:

• an RF low-noise amplifier coupled to an antenna for receiving digital data in an RF analog signal;
• an RF-envelope detector coupled to the RF low-noise amplifier for downmixing the RF analog signal and for outputting a baseband analog signal;
• a semi-logarithmic baseband transimpedance amplifier coupled to the RF-envelope detector;
• a baseband low-pass filter having an input coupled to the semi-logarithmic baseband transimpedance amplifier and having an output terminal;
• a fast-settling threshold estimator having an input terminal coupled to the output terminal of the baseband low-pass filter and having an output terminal for outputting a fast-settling threshold voltage;
• and
• a bit slicer having a first input terminal coupled to the output terminal of the baseband low-pass filter and a second input terminal coupled to the output terminal of the fast-settling threshold estimator, wherein the bit slicer outputs a binary signal responsive to the digital data in the analog RF signal and responsive to the fast-settling threshold voltage.