Low phase noise phase locked loop

A signal generator, comprising:

• a controlled oscillator circuit configured to generate an output signal having an output signal frequency based on a control input signal;
• a frequency divider circuit configured to produce a divided frequency output having a frequency equal to the output signal frequency divided by a value;
• a phase frequency detector circuit configured to produce a phase error signal based on a phase difference between the divided frequency output and a frequency reference signal;
• a Phase Locked Loop (PLL) filter circuit configured to generate a low pass filtered error signal with a frequency based on low pass filtering the phase error signal;
• a tunable Inductor-Capacitor (LC) time reference circuit comprising an LC-tank circuit having a resonant frequency based on the low pass filtered error signal, the tunable LC time reference circuit configured to receive the output signal, generate a time reference signal, and introduce a determined time delay relative to the output signal when the output signal frequency is at the resonant frequency;
• and
• a time error detector circuit configured to determine a filtered time error signal indicating a time error between the output signal and the time reference signal, wherein the control input signal is based on the filtered time error signal.