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US 2026/0205124 A1Published application
Clock data recovery circuit and apparatus including the same
AssigneesSamsung Electronics Co., Ltd., Seoul National University R&Db Foundation
InventorsWooseok CHOI, Jihee KIM
Life of this patent
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Abstract
A clock data recovery circuit including: a sampler to sample a comparison result between an input data signal and multiple reference voltages or to sample the input data signal based on a recovered clock signal; and a control circuit to output a control signal for controlling a phase of the recovered clock signal based on a K signal, an up signal, and a down signal.
Claims18
A clock data recovery circuit comprising:
- a control circuit configured to output a control signal for controlling a phase of a recovered clock signal, and
- a sampler, which comprises:
- a first sampler configured to output a data sample signal based on the recovered clock signal, the data sample signal indicating a first comparison result between a voltage level of an input data signal and a third reference voltage;
- a second sampler configured to output an error signal based on the recovered clock signal, the error signal indicating a second comparison result between a voltage level of the input data signal and a first reference voltage;
- and
- a third sampler configured to output an eye monitoring signal based on the recovered clock signal or an edge of a delayed recovered clock signal, the eye monitoring signal indicating a third comparison result between a voltage level of the input data signal and a second reference voltage,
- wherein the control circuit comprises:
- a phase detector configured to output an up signal or a down signal based on the data sample signal and the error signal;
- a first logic configured to output a K signal based on the data sample signal and the eye monitoring signal;
- a second logic configured to output a phase error signal based on the K signal, the up signal, and the down signal;
- and
- a phase interpolator (PI) code generator configured to output the control signal based on the phase error signal.
9 more elements
An apparatus comprising:
- a reception circuit;
- and
- a transmission circuit configured to transmit an input data signal to the reception circuit through a channel,
- wherein the reception circuit comprises:
- a control circuit configured to output a control signal for controlling a phase of a recovered clock signal, and
- a sampler, which comprises:
- a first sampler configured to output a data sample signal based on the recovered clock signal, the data sample signal indicating a first comparison result between a voltage level of an input data signal and a third reference voltage;
- a second sampler configured to output an error signal based on the recovered clock signal, the error signal indicating a second comparison result between a voltage level of the input data signal and a first reference voltage;
- and
- a third sampler configured to output an eye monitoring signal based on the recovered clock signal or an edge of a delayed recovered clock signal, the eye monitoring signal indicating a third comparison result between a voltage level of the input data signal and a second reference voltage,
- wherein the control circuit comprises:
- a phase detector configured to output an up signal or a down signal based on the data sample signal and the error signal;
- a first logic configured to output a K signal based on the data sample signal and the eye monitoring signal;
- a second logic configured to output a phase error signal based on the K signal, the up signal, and the down signal;
- and
- a phase interpolator (PI) code generator configured to output the control signal based on the phase error signal.
13 more elements
Dependencies are inferred from the claim text.