Accurate synchronous analogue counter

An analog counter of the number of events in at least one logic input signal over a counting period, said counting period comprising a set of detection cycles during which an event in the logic input signal can be detected, wherein the analog counter comprises:

• a circuit for periodically generating a calibrated quantity of charge for each detection cycle;
• an integration capacitor configured to store said calibrated quantity of charge during each detection cycle of the counting period for which an event in the logic input signal is detected so that an output voltage, across the integration capacitor, is representative of the number of events of the logic input signal detected during the counting period;
• a circuit for switching the calibrated quantity of charge controlled by the logic input signal to store said calibrated quantity of charge into the integration capacitor only when an event is detected on the logic input signal;
• a circuit for generating control signals of the analog counter;
• a circuit for resetting the output voltage across the integration capacitor so as to reset the counting;
• the circuit for periodically generating a calibrated quantity of charge comprising:
• an injection capacitor configured to store the calibrated quantity of charge during each detection cycle and connected by one of its terminals to a first bias voltage;
• an injection control transistor having its source connected to the other terminal of the injection capacitor, having its gate connected to a control voltage, and having its drain connected to an injection node;
• a charge transistor having its source connected to a second bias voltage and having its drain connected to the injection node;
• and
• a transfer transistor having its source connected to the injection node and having its drain connected to a switching node;
• the gate of the two charge and transfer transistors being controlled by clock signals in phase opposition so as to charge said injection capacitor, and then to transfer the charges accumulated in said injection capacitor to the switching circuit;
• the control signal generation circuit being configured to control the control voltage and the clock signals so as to successively generate the following phases at each detection cycle:
• an initialization phase during which the injection control transistor and the charge transistor are on while the transfer transistor is off;
• a precharge phase during which the injection control transistor and the transfer transistor are on while the charge transistor is off, the control voltage being set to a first value;
• and
• a charge phase during which the injection control transistor and the transfer transistor are on while the charge transistor is off, the control voltage being set to a second value.