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US 2026/0205010 A1Published application
Charge pump circuit and charge pump device
AssigneeeMemory Technology Inc.
InventorZHE-YI LIN
Life of this patent
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Abstract
A charge pump circuit includes a first pump unit and a second pump unit. The first pump unit generates a pumped voltage according to an input voltage, a first clock signal, and a second clock signal. The first clock signal and the second clock signal are in phase, and the second clock signal has a higher swing than that of the first clock signal. The second pump unit has a structure similar to that of the first pump unit, and the first and the second pump units alternatively output a pumped voltage according to the input voltage. Transistors in the first pump unit and the second pump unit are operating within their safe operation area (SOA) and are disposed in two wells that are biased independently.
Claims20
A charge pump circuit comprising:
- an input terminal configured to receive an input voltage;
- an output terminal configured to output an output voltage;
- a first pump unit comprising:
- a first capacitor having a first terminal configured to receive a first clock signal, and a second terminal;
- a second capacitor having a first terminal configured to receive a second clock signal, and a second terminal;
- a first transistor having a first terminal coupled to the input terminal, a second terminal coupled to the second terminal of the first capacitor, and a control terminal coupled to the second terminal of the second capacitor;
- a second transistor having a first terminal coupled to the second terminal of the second capacitor, a second terminal coupled to the second terminal of the first transistor, and a control terminal;
- and
- a first auxiliary control unit coupled to the control terminal of the second transistor, and configured to turn on the second transistor when the first clock signal is at a first high voltage, and turn off the second transistor when the first clock signal is at a low voltage;
- a first output transistor having a first terminal coupled to the second terminal of the first transistor, a second terminal coupled to the output terminal, and a control terminal;
- a second pump unit comprising:
- a third capacitor having a first terminal configured to receive a third clock signal, and a second terminal;
- a fourth capacitor having a first terminal configured to receive a fourth clock signal, and a second terminal;
- a third transistor having a first terminal coupled to the input terminal, a second terminal coupled to the second terminal of the third capacitor and the control terminal of the first output transistor, and a control terminal coupled to the second terminal of the fourth capacitor;
- a fourth transistor having a first terminal coupled to the second terminal of the fourth capacitor, a second terminal coupled to the second terminal of the third transistor, and a control terminal;
- and
- a second auxiliary control unit coupled to the control terminal of the fourth transistor, and configured to turn on the fourth transistor when the third clock signal is at the first high voltage, and turn off the fourth transistor when the third clock signal is at the low voltage;
- and
- a second output transistor having a first terminal coupled to the second terminal of the third transistor, a second terminal coupled to the output terminal, and a control terminal coupled to the second terminal of the first transistor;
- wherein the first clock signal and the second clock signal are in phase, the third clock signal and the fourth clock signal are in phase, the first clock signal and the third clock signal are out of phase, the second clock signal has a higher swing than that of the first clock signal, and the fourth clock signal has a higher swing than that of the third clock signal;
- wherein the first transistor and the second transistor are disposed in a first well, and the third transistor and the fourth transistor are disposed in a second well.
18 more elements
A charge pump device comprising:
- a plurality stages of charge pump circuit, and an input terminal of a latter stage being connected to an output terminal of a previous stage;
- wherein a first stage of charge pump circuit comprises:
- an input terminal configured to receive an input voltage;
- an output terminal configured to output an output voltage;
- a first pump unit comprising:
- a first capacitor having a first terminal configured to receive a first clock signal, and a second terminal;
- a second capacitor having a first terminal configured to receive a second clock signal, and a second terminal;
- a first transistor having a first terminal coupled to the input terminal of the first stage of charge pump circuit, a second terminal coupled to the second terminal of the first capacitor, and a control terminal coupled to the second terminal of the second capacitor;
- a second transistor having a first terminal coupled to the second terminal of the second capacitor, a second terminal coupled to the second terminal of the first transistor, and a control terminal;
- and
- a first auxiliary control unit coupled to the control terminal of the second transistor, and configured to turn on the second transistor when the first clock signal is at a first high voltage, and turn off the second transistor when the first clock signal is at a low voltage;
- a first output transistor having a first terminal coupled to the second terminal of the first transistor, a second terminal coupled to the output terminal of the first stage of charge pump circuit, and a control terminal;
- a second pump unit comprising:
- a third capacitor having a first terminal configured to receive a third clock signal, and a second terminal;
- a fourth capacitor having a first terminal configured to receive a fourth clock signal, and a second terminal;
- a third transistor having a first terminal coupled to the input terminal of the first stage of charge pump circuit, a second terminal coupled to the second terminal of the third capacitor and the control terminal of the first output transistor, and a control terminal coupled to the second terminal of the fourth capacitor;
- a fourth transistor having a first terminal coupled to the second terminal of the fourth capacitor, a second terminal coupled to the second terminal of the third transistor, and a control terminal;
- and
- a second auxiliary control unit coupled to the control terminal of the fourth transistor, and configured to turn on the fourth transistor when the third clock signal is at the first high voltage, and turn off the fourth transistor when the third clock signal is at the low voltage;
- and
- a second output transistor having a first terminal coupled to the second terminal of the third transistor, a second terminal coupled to the output terminal of the first stage of charge pump circuit, and a control terminal coupled to the second terminal of the first transistor;
- wherein the first clock signal and the second clock signal are in phase, the third clock signal and the fourth clock signal are in phase, the first clock signal and the third clock signal are out of phase, the second clock signal has a higher swing than that of the first clock signal, and the fourth clock signal has a higher swing than that of the third clock signal;
- wherein the first transistor and the second transistor are disposed in a first well, and the third transistor and the fourth transistor are disposed in a second well.
20 more elements
Dependencies are inferred from the claim text.