Charge trapping flash nor memory in memory systems

A memory system, comprising:

• a not-or (NOR) memory device;
• and
• processing circuitry coupled with the NOR memory device and configured to cause the memory system to:
• communicate, from the processing circuitry to the NOR memory device, one or more read commands directed to one or more model parameters associated with an artificial intelligence (AI) model, wherein the NOR memory device comprises a plurality of charge trapping flash NOR memory cells;
• obtain, at the processing circuitry from the NOR memory device via a first interface, the one or more model parameters in response to the one or more read commands;
• and
• execute, at the processing circuitry, an AI inference operation using the one or more model parameters in response to obtaining the one or more model parameters.

A method for operating a memory system, comprising:

• communicating, from processing circuitry of the memory system to a not-or (NOR) memory device of the memory system, one or more read commands directed to one or more model parameters associated with an artificial intelligence (AI) model, wherein the NOR memory device comprises a plurality of charge trapping flash NOR memory cells;
• obtaining, at the processing circuitry from the NOR memory device via a first interface, the one or more model parameters in response to the one or more read commands;
• and
• executing, at the processing circuitry, an AI inference operation using the one or more model parameters in response to obtaining the one or more model parameters.