Memory device, memory array and operation method of the same
AssigneeMacronix International Co., Ltd.
InventorsYu-Hsuan LIN, Feng-Min LEE, Yu-Yu LIN
Life of this patent
Estimating the term…
Abstract
A memory device includes a memory cell. The memory cell includes a first switch element, a second switch element and a storage element. The first switch element configured to receive a write bit line signal, and coupled to a storage node. The second switch element configured to receive a read bit line signal, and coupled to the storage node. The a storage element coupled to the storage node, and configured to receive a voltage signal and store a first data bit, wherein the memory cell is configured to store a second data bit different from the first data bit at the storage node.
Claims20
A memory device, comprising a memory cell, the memory cell comprising:
- a first switch element configured to receive a write bit line signal, and coupled to a storage node;
- a second switch element configured to receive a read bit line signal, and coupled to the storage node;
- and
- a storage element coupled to the storage node, and configured to receive a voltage signal and store a first data bit,
- wherein the memory cell is configured to store a second data bit different from the first data bit at the storage node.
A memory array, comprising a plurality of memory cells, the plurality of memory cells comprising:
- a first memory cell configured to receive a first read bit line signal, a first read signal and a first voltage signal;
- a second memory cell configured to receive at least one of the first read bit line signal and the first read signal;
- and
- a third memory cell configured to receive at least one of the first read bit line signal, the first read signal and the first voltage signal,
- wherein when a first data bit is written into the first memory cell, the first voltage signal has a first voltage level,
- when a second data bit is written into the first memory cell, in response to the second data bit having a first logic value, the first voltage signal has a second voltage level larger than the first voltage level, and
- when the second data bit is written into the first memory cell, in response to the second data bit having a second logic value, the first voltage signal has the first voltage level.
An operation method of a memory device, comprising:
- receiving a write bit line signal by a first switch element coupled to a storage node;
- receiving a read bit line signal by a second switch element coupled to the storage node;
- receiving a voltage signal by a storage element coupled to the storage node;
- storing a first data bit by the storage element;
- and
- storing a second data bit different from the first data bit at the storage node.
Dependencies are inferred from the claim text.