Memory device and operating method thereof

An operating method of a memory device, comprising:

• programming a memory device to a first state;
• counting fail bits of the memory device programmed to the first state for each reference resistor, using a plurality of resistors having different values from each other;
• programming the memory device to a second state;
• counting fail bits of the memory device programmed to the second state for each reference resistor, using the plurality of resistors;
• selecting a reference resistor among the plurality of resistors, based on the counting results associated with the first state and the counting results associated with the second state;
• discriminating a value of a first program current for the memory device based on the value of the selected reference resistor;
• discriminating a value of a second program current for the memory device, based on the value of the first program current and a fail bit reference value indicating a percentage of error bits allowable in the memory device;
• discriminating a value of a first read current for the memory device based on the value of the selected reference resistor;
• and
• discriminating a value of a second read current for the memory device, based on the value of the first read current and a first offset value obtained by subtracting the value of the first program current from the value of the second program current.

A memory device comprising:

• a memory cell array including a first region, and a second region configured to store a value of a program current discriminated, based on a value of a reference resistor for distinguishing between a parallel state and an anti-parallel state of a programmed memory cell and a fail bit reference value indicating a percentage of error bits allowable in the memory cell array, and a value of a read current discriminated based on the value of the reference resistor and the value of the program current;
• and
• a sensing circuit configured to generate the read current and perform a read operation on the first region based on the read current,
• the value of the program current including a value of a second program current generated by adding a first offset value discriminated based on the fail bit reference value to a value of a first program current discriminated based on the value of the reference resistor, and
• the value of the read current including a value of a first read current discriminated based on the value of the reference resistor, and a value of a second read current generated by adding a second offset value generated based on the first offset to the value of the first read current,
• a percentage of error bits generated based on the value of the second program current does not exceed the fail bit reference value, and
• a ratio of the first offset value to the value of the first program current is equal to a ratio of the second offset value to the value of the first read current.