Scalable mirror driver circuitry and light protection for light modulator

An integrated circuit comprising:

• a substrate;
• a two-dimensional array of memory cells on the substrate;
• a two-dimensional array of pixel elements positioned over the array of memory cells, each pixel element of the array of pixel elements electrically connected to an output of a respective memory cell of the array of memory cells;
• a plurality of metal layers arranged between the array of memory cells and the array of pixel elements;
• control circuitry including circuit elements formed in one or more metal layers of the plurality of metal layers, the circuit elements including at least one transistor and the control circuitry operably coupled to the array of memory cells;
• and
• a light-blocking apparatus including
• one or more guard rings formed in the one or more metal layers and at least partially surrounding a corresponding one or more respective circuit elements in the one or more metal layers,
• at least one isolation well coupled to the at least one transistor, and
• an isolation wall operable to block stray carriers from reaching the circuit elements, the stray carriers being induced by light incident on the integrated circuit with an intensity above a threshold lumen level.

A light modulator comprising:

• a substrate;
• a two-dimensional array of memory cells on the substrate;
• a two-dimensional array of pixel elements positioned over the array of memory cells, each pixel element of the array of pixel elements electrically connected to an output of a respective memory cell of the array of memory cells, the array of pixel elements arranged into a plurality of groups with each group including one or more pixel elements;
• and
• control circuitry coupled to the array of memory cells and to the array of pixel elements, the control circuitry including
• a data interface configurable to receive image data, the control circuitry configurable to write the image data to the array of memory cells to control operational states of the array of pixel elements, and
• adjustable reset control circuitry including
• a plurality of banks of pixel block drivers configurable to provide respective control voltages to respective individual groups and each bank of pixel block drivers in the plurality of banks of pixel block drivers including a bank of reset capacitors and an adjustable number of one or more reset drivers,
• a signal bus coupled to the plurality of banks of pixel block drivers,
• an adjustable number of supply voltage generators selectively coupled to the signal bus and configurable to provide a supply voltage to the signal bus,
• a plurality of level shifters coupled between the signal bus and the plurality of banks of pixel block drivers, individual level shifters configurable to adjust a voltage level of the supply voltage supplied to a respective one of the plurality of banks of pixel block drivers, and
• a plurality of buffers coupled between the plurality of level shifters and the plurality of banks of pixel block drivers.