Methods and apparatus to implement vector processing units
AssigneeOpenchip & Software Technologies S.L.
InventorsErich Ludwig Focht, Francesc Guim Bernat, Violante Moschiano, Satoru Tagaya
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Abstract
Systems, apparatus, articles of manufacture, and methods are disclosed. An example vector processing unit (VPU) comprises: a plurality of vector lanes, the vector lanes able to collectively process an instruction of a first length, and sequencer circuitry to: distribute a second instruction to a first subset of the vector lanes, the second instruction having a second length shorter than the first length, and distribute a third instruction to a second subset of the vector lanes, the second subset to execute the third instruction in parallel with the execution of the second instruction by the first subset of vector lanes.
Claims21
A vector processing unit (VPU) comprising:
- a plurality of vector lanes, the vector lanes able to collectively process a first instruction of a first length;
- and
- sequencer circuitry to:
- distribute a second instruction to a first subset of the vector lanes, the second instruction having a second length shorter than the first length;
- and
- distribute a third instruction to a second subset of the vector lanes, the second subset of the vector lanes to execute the third instruction in parallel with the execution of the second instruction by the first subset of the vector lanes.
A system comprising:
- a software application to generate a first instruction having a first length and a second instruction having a second length;
- and
- a vector processing unit (VPU) to include:
- a plurality of vector lanes, the vector lanes to collectively process a third instruction of a third length that is longer than the first length and the second length;
- and
- sequencer circuitry to:
- distribute the first instruction to a first subset of the vector lanes;
- and
- distribute the second instruction to a second subset of the vector lanes, the second subset of the vector lanes to execute the second instruction in parallel with the execution of the second instruction by the first subset of the vector lanes.
A system comprising:
- a first operating system to generate a first instruction having a first length;
- a second operating system to generate a second instruction having a second length;
- a hypervisor to provide the first instruction and the second instruction to a vector processing unit (VPU);
- and
- the VPU including:
- a plurality of vector lanes, the vector lanes to collectively process a third instruction of a third length that is longer than the first length and the second length;
- and
- sequencer circuitry to:
- distribute the first instruction to a first subset of the vector lanes;
- and
- distribute the second instruction to a second subset of the vector lanes, the second subset of the vector lanes to execute the second instruction in parallel with the execution of the second instruction by the first subset of the vector lanes.
(canceled)
Dependencies are inferred from the claim text.