Cache prefetching employing hit prediction
AssigneeInternational Business Machines Corporation
InventorsDominic DiTomaso, David Trilla Rodríguez, Alper Buyuktosunoglu, Craig R. Walters, Ram Sai Manoj Bamdhamravuri
Life of this patent
Estimating the term…
Abstract
A processor set has an associated cache memory. A prefetch unit of the processor set generates a prefetch request. The prefetch unit determines whether the prefetch request is likely to miss in the cache memory. The prefetch unit issues the prefetch request based on determining that the prefetch request is likely to miss in the cache memory and otherwise discards the prefetch request. The prefetch request can be a data prefetch request or an instruction prefetch request.
Claims20
A computer-implemented method of prefetching, the method comprising:
- a prefetch unit of a processor core generating a prefetch request, the processor core having an associated cache memory and a processor core;
- the prefetch unit determining whether the prefetch request is likely to miss in the cache memory;
- and
- the prefetch unit issuing the prefetch request based on determining that the prefetch request is likely to miss in the cache memory and otherwise discarding the prefetch request,
- wherein
- the processor core includes a history-based hit/miss predictor;
- and
- the determining includes determining whether the prefetch request is likely to miss in the cache memory based on an entry in the history-based hit/miss predictor, wherein the prefetch request is likely to miss in the cache memory responsive to a counter value of the history-based hit/miss predictor being less than a threshold.
(canceled)
A processor set, comprising:
- a cache memory;
- and
- a processor core including a prefetch circuit having a hit/miss predictor, wherein the prefetch circuit is configured to perform operations including:
- generating a prefetch request;
- determining by reference to the hit/miss predictor whether the prefetch request is likely to miss in the cache memory;
- and
- issuing the prefetch request based on determining that the prefetch request is likely to miss in the cache memory and otherwise discarding the prefetch request,
- wherein:
- the hit/miss predictor is a history-based hit/miss predictor;
- and
- the determining includes determining whether the prefetch request is likely to miss in the cache memory based on an entry in the history-based hit/miss predictor.
(canceled)
A design structure tangibly embodied in a non-transitory machine-readable storage device for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
- a processor set, including:
- a cache memory;
- and
- a processor core including a prefetch circuit having a hit/miss predictor, wherein the prefetch circuit is configured to perform operations including:
- generating a prefetch request;
- determining by reference to the hit/miss predictor whether the prefetch request is likely to miss in the cache memory;
- and
- issuing the prefetch request based on determining that the prefetch request is likely to miss in the cache memory and otherwise discarding the prefetch request,
- wherein:
- the hit/miss predictor is a history-based hit/miss predictor;
- and
- the determining includes determining whether the prefetch request is likely to miss in the cache memory based on an entry in the history-based hit/miss predictor.
(canceled)
Dependencies are inferred from the claim text.