Immediate offset of load store and atomic instructions

A method comprising:

• receiving a memory access message at memory access circuitry configured to facilitate access to memory of a graphics processing device, the memory access message received from a processing resource of the graphics processing device, wherein the memory access message includes a memory address and an immediate offset value;
• performing a bounds check for the memory address as adjusted according to the immediate offset value, wherein the bounds check is performed for a memory allocation to be accessed via the memory access message;
• generating one or more memory access requests including the memory address as adjusted according to the immediate offset value in response to determination by the memory access circuitry that the memory access message is associated with an in-bound memory access;
• and
• submitting the one or more memory access requests to a cache or memory interface.

A data processing system comprising:

• a host interface;
• a memory device;
• and
• a graphics processor device coupled with the host interface and the memory device, the graphics processor device comprising a processing resource including a register file, a cache, and memory access circuitry to process memory access messages received from the processing resource, wherein to process the memory access messages, the memory access circuitry is configured to:
• receive a memory access message from the processing resource, wherein the memory access message includes a memory address and an immediate offset value;
• perform a bounds check for the memory address as adjusted according to the immediate offset value, wherein the bounds check is performed for a memory allocation to be accessed via the memory access message;
• generate one or more memory access requests including the memory address as adjusted according to the immediate offset value in response to determination by the memory access circuitry that the memory access message is associated with an in-bound memory access;
• and
• submit the one or more memory access requests to a cache or memory interface.