System and method for controlling power supply

A method for controlling power supply of a computing system that includes one or more memories, one or more processors, a first programmable logic device coupled to the first circuit board, a second programmable logic device coupled to the second circuit board, and a first power supply and a second power supply that are coupled to the second circuit board, the method comprising:

• detecting a first triggering event to power off the second circuit board, comprising:
• detecting that a utilization rate of the one or more processors is below a first processor utilization rate threshold for a first time period, or
• detecting that a utilization rate of the one or more memories is below a first memory utilization rate threshold for a second time period;
• and
• in response to detecting the first triggering event:
• transmitting a first message to power off the second circuit board to the first programmable logic device that is coupled to the first circuit board,
• wherein transmitting the first message to power off the second circuit board to the first programmable logic device causes the first programmable logic device to transmit a first command that powers off the first power supply, to the second programmable logic device that is coupled to the second circuit board, and
• wherein transmitting the first command to the second programmable logic device causes the second programmable logic device to turn off the first power supply that is coupled to the second circuit board.

A method for controlling power supply of a computing system that includes one or more memories, one or more processors, a first programmable logic device coupled to the first circuit board, a second programmable logic device coupled to the second circuit board, and a first power supply and a second power supply that are coupled to the second circuit board, the method comprising:

• detecting a second triggering event to power on the second circuit board, comprising:
• detecting that a utilization rate of the one or more processors is beyond a second processor utilization rate threshold for a first duration, or
• detecting that a utilization rate of the one or more memories is beyond a second memory utilization rate threshold for a second duration;
• and
• in response to detecting the second triggering event:
• controlling the second power supply to turn on the second power supply that is coupled to the second circuit board;
• transmitting a message that powers on the second circuit board, to the first programmable logic device;
• wherein transmitting the message that powers on the second circuit board to the first programmable logic device causes the first programmable logic device to transmit a command that powers on the first power supply, to the second programmable logic device that is coupled to the second circuit board, and
• wherein transmitting the command to the second programmable logic device causes the second programmable logic device to turn on the first power supply that is coupled to the second circuit board.