Testing integrated circuits via scan chain compression
AssigneeInternational Business Machines Corporation
InventorNilabha Dev
Life of this patent
Estimating the term…
Abstract
A method for performing integrated circuit testing is presented. A compactor is generated using explicit expander graph construction. A decompressor and the generated compactor are inserted within a device-under-tested (DUT). After feeding a compressed test pattern into the DUT, the compressed test pattern is expanded via the decompressor into internal scan-ins within the DUT. Subsequently, the internal scan-out data is compressed into compressed output vectors using the generated compactor. After shifting out from the DUT, the compressed output vectors are compared to a set of desired outputs in order to determine a pass/fail status of the DUT.
Claims15
A method comprising:
- generating a compactor by using explicit expander graphs;
- inserting said generated compactor and a decompressor within a device-under-test (DUT),
- feeding a compressed test pattern into said DUT;
- expanding said compressed test pattern via said decompressor into internal scan-ins within said DUT;
- compressing internal scan-outs data into compressed output vectors via said generated compactor;
- shifting out said compressed output vectors from said DUT;
- and
- comparing said compressed output vectors to a set of desired outputs in order to determine a pass/fail status of said DUT.
A computer program product for performing integrated circuit testing, said computer program product comprising a computer readable storage medium having program instructions embodied therein, said program instructions executable by a computer to cause said computer to perform:
- generating a compactor by using explicit expander graphs;
- inserting said generated compactor and a decompressor within a device-under-test (DUT),
- feeding a compressed test pattern into said DUT;
- expanding said compressed test pattern via said decompressor into internal scan-ins within said DUT;
- compressing internal scan-outs data into compressed output vectors via said generated compactor;
- shifting out said compressed output vectors from said DUT;
- and
- comparing said compressed output vectors to a set of desired outputs in order to determine a pass/fail status of said DUT.
A data processing system for testing integrated circuits, said data processing system comprising:
- processing circuitry;
- and
- a storage device coupled to said processor circuitry, wherein said storage device includes program code executable by said processing circuitry to cause said data processing system to perform:
- generating a compactor via explicit expander graphs;
- inserting said generated compactor and a decompressor within a device-under-test (DUT),
- feeding a compressed test pattern into said DUT;
- expanding said compressed test pattern via said decompressor into internal scan-ins within said DUT;
- compressing internal scan-outs data into compressed output vectors via said generated compactor;
- shifting out said compressed output vectors from said DUT;
- and
- comparing said compressed output vectors to a set of desired outputs in order to determine a pass/fail status of said DUT.
Dependencies are inferred from the claim text.