A wafer-level package and a method for forming the wafer-level package

Abstract

A wafer-level package is described. In an embodiment, the wafer-level package (100) comprises: a substrate (102) having electrically conductive interconnects embedded within the substrate (102), the substrate (102) having a top substrate surface and a bottom substrate surface opposite to the top substrate surface, the bottom substrate surface being adapted to be provided on a printed circuit board (PCB); a first integrated circuit die (104) having an active surface wherein the first integrated circuit die is provided adjacent to an edge portion of a perimeter of the substrate (102); a mold (108) adapted to hold the first integrated circuit die (104) and the substrate (102) so that the active surface of the first integrated circuit die (104) is in a same plane as the top substrate surface; a first redistribution layer (110) having electrically conductive interconnects embedded within the first redistribution layer (110), the first redistribution layer (110) being formed on the active surface of the first integrated circuit die (104) and the top substrate surface; and a second integrated circuit die (112) provided on the first redistribution layer (110), the second integrated circuit die (112) being electrically connected to the first integrated circuit die (104) via the first redistribution layer (110). Embodiments in relation to a method (200) for forming the wafer-level package are also described.

Dependencies are inferred from the claim text.