Power plane between stacked fets

A semiconductor structure comprising:

• a first stack of transistors in a first transistor cell, the first stack of transistors including a first top transistor and a first bottom transistor;
• a second stack of transistors in a second transistor cell, the second stack of transistors including a second top transistor and a second bottom transistor, the second transistor cell being adjacent to a first side of the first transistor cell;
• a third stack of transistors in a third transistor cell, the third stack of transistors including a third top transistor and a third bottom transistor, the third transistor cell being adjacent to a second side of the first transistor cell, the second side opposing the first side;
• a first power plane between the first top transistor and the first bottom transistor and between the second top transistor and the second bottom transistor;
• and
• a second power plane between the first top transistor and the first bottom transistor and between the third top transistor and the third bottom transistor,
• wherein the second bottom transistor is underneath the first power plane and the third top transistor is above the second power plane.

A semiconductor structure comprising:

• a first stack of transistors in a first transistor cell, the first stack of transistors including a first top transistor and a first bottom transistor;
• a second stack of transistors in a second transistor cell, the second stack of transistors including a second top transistor and a second bottom transistor, the second transistor cell being adjacent to the first transistor cell;
• a third stack of transistors in a third transistor cell, the third stack of transistors including a third top transistor and a third bottom transistor, the third transistor cell being adjacent to the first transistor cell;
• a first power plane between the first top transistor and the first bottom transistor and between the second top transistor and the second bottom transistor;
• and
• a second power plane between the first top transistor and the first bottom transistor and between the third top transistor and the third bottom transistor.