Memory devices with multiple tracks forming access line and methods for manufacturing the same

A semiconductor device, comprising:

• a first memory array including a plurality of first memory cells arranged over a plurality of first columns and a plurality of first rows, wherein each of the plurality of first rows includes at least a first word line, and each of the plurality of first columns includes at least a first bit line and a first source line;
• a first strap region disposed next to the first memory array along a lateral direction;
• and
• a second strap region disposed next to the first strap region along the lateral direction;
• wherein a plurality of first via structures are formed in the first strap region, and the plurality of first via structures are configured to electrically connect a first metal track and a second metal track operatively constituting at least a part of each of the first source lines;
• and
• wherein a plurality of second via structures are formed in the second strap region, and the plurality of second via structures are configured to electrically connect a third metal track and a fourth metal track operatively constituting at least a part of each of the first bit lines.

A method for forming memory devices, comprising:

• forming a plurality of transistors over a first region of a substrate, wherein the plurality of transistors operatively form portions of a plurality of memory cells, respectively;
• and
• forming a plurality of metallization layers over the plurality of transistors;
• wherein a first one of the plurality of metallization layers includes a first metal track, a second one of the plurality of metallization layers includes a second metal track, a third one of the plurality of metallization layers includes a third metal track, and a fourth one of the plurality of metallization layers includes a fourth metal track;
• and
• wherein the first metal track and the second metal track are electrically connected to each other and collectively serve as a first access line for the plurality of memory cells, and the third metal track and the fourth metal track are electrically connected to each other and collectively serve as a second access line for the plurality of memory cells.