Iii-nitride transistor comprising a plurality of isolation regions

A power transistor comprising:

• a source terminal;
• a drain terminal;
• a gate terminal;
• a heterojunction formed between two III-nitride semiconductor layers, the heterojunction being configured to allow the formation of a two-dimensional carrier gas at the heterojunction and thereby define an active area of the power transistor;
• and
• a plurality of isolation regions located inside a boundary of the active area, the plurality of isolation regions being configured to prevent the formation of the two-dimensional carrier gas inside the plurality of isolation regions;
• wherein the plurality of isolation regions comprise a plurality of doped III-nitride regions, each doped III-nitride region of the plurality of doped III-nitride regions configured to be biased to a potential;
• wherein the source terminal, the drain terminal, and the gate terminal are laterally spaced apart in a first direction, the gate terminal being located between the source terminal and the drain terminal;
• and
• wherein the isolation regions are spaced apart from one another in a second direction, perpendicular to the first direction.