Successive approximation analog-to-digital converter performing hybrid redundancy operation

A successive approximation analog-to-digital converter, comprising:

• a resistor digital-to-analog converter comprising a plurality of series-connected resistors connected between an upper reference voltage and a lower reference voltage, and configured to provide a plurality of non-binary weighted divided voltages;
• a first capacitor digital-to-analog converter, configured to:
• perform a non-binary Most Significant Bit (MSB) conversion process including a first redundancy bit, using a first redundancy capacitor and a first non-binary weighted MSB capacitor array, for an analog input voltage;
• and
• perform a non-binary Least Significant Bit (LSB) conversion process including a second redundancy bit, using a first LSB capacitor to which one of the plurality of non-binary weighted divided voltages is applied, thereby sequentially generating a first capacitor digital-to-analog converter output voltage;
• a second capacitor digital-to-analog converter configured to sequentially generate a second capacitor digital-to-analog converter output voltage, using a second redundancy capacitor, a second non-binary weighted MSB capacitor array, and a second LSB capacitor;
• a first capacitor multiplexer configured to provide a voltage selected from the analog input voltage, the upper reference voltage, the lower reference voltage, and the plurality of non-binary weighted divided voltages to the first capacitor digital-to-analog converter;
• a second capacitor multiplexer configured to provide a voltage selected from the upper reference voltage, the lower reference voltage, and the plurality of non-binary weighted divided voltages to the second capacitor digital-to-analog converter;
• a first resistor multiplexer configured to select from the plurality of non-binary weighted divided voltages and provide to the first capacitor multiplexer;
• a second resistor multiplexer configured to select from the plurality of non-binary weighted divided voltages and provide to the second capacitor multiplexer;
• a comparator configured to compare the first capacitor digital-to-analog converter output voltage and the second capacitor digital-to-analog converter output voltage;
• and
• an SAR logic configured to control the first capacitor multiplexer, the second capacitor multiplexer, the first resistor multiplexer, and the second resistor multiplexer according to an output of the comparator.

A successive approximation analog-to-digital converter, comprising:

• a first capacitor digital-to-analog converter configured to perform a non-binary conversion process including a redundancy bit, using a first redundancy capacitor and a first non-binary weighted capacitor array, for an analog input voltage, thereby sequentially generating a first capacitor digital-to-analog converter output voltage;
• a second capacitor digital-to-analog converter configured to sequentially generate a second capacitor digital-to-analog converter output voltage, using a second redundancy capacitor, and a second non-binary weighted capacitor array;
• and
• a comparator, configured to compare the first capacitor digital-to-analog converter output voltage and the second capacitor digital-to-analog converter output voltage,
• wherein based on a number of digital codes being increased by a number of redundancy LSBs added by the first redundancy capacitor, the non-binary conversion process is performed by shifting a group of digital codes, including those added by the redundancy LSBs, within a range of the added redundancy LSBs,
• wherein based on the non-binary conversion process being completed, the shifted redundancy LSBs are subtracted from the digital code, and the redundancy bit is removed.