US 2026/0197007 A1 · Phase-Locked Loop with Synchronized Clock Signals

Abstract

A phase-locked loop. The phase-locked loop has a phase ascertaining unit for detecting a phase of a reference signal and outputting a measurement signal, a phase deviation ascertaining unit generating an error signal from the measurement signal and a target signal, a loop filter for filtering the error signal, a modulator unit for modulating the filtered error signal and generating a tune signal, and an oscillator for generating an output signal from the tune signal. A feedback signal formed from an output signal of the phase-locked loop is supplied to the phase ascertaining unit. The phase-locked loop includes: a divider unit configured to generate a modulator clock pulse signal from an oscillator clock pulse signal of the oscillator and to supply the modulator clock pulse signal to the modulator unit, and a sampler unit configured to detect a mismatch between the reference signal and the modulator clock pulse signal.

Claims11

Dependent claims

1-10. (canceled)

A phase-locked loop, comprising:

a phase ascertaining unit configured to detect a phase of a reference signal and to output a measurement signal;
a phase deviation ascertaining unit configured to generate an error signal from the measurement signal and from a target signal;
a loop filter configured to filter the error signal;
a modulator unit configured to modulate the filtered error signal and to generate a tune signal;
and
an oscillator configured to generate an output signal from the tune signal;
wherein a feedback signal derived from an output signal of the phase-locked loop is supplied to the phase ascertaining unit;
and
wherein the phase-locked loop further comprises:
a divider unit configured to create a modulator clock pulse signal from an oscillator clock pulse signal of the oscillator and to supply the modulator clock pulse signal to the modulator unit, and
a sampler unit configured to detect a mismatch between the reference signal and the modulator clock pulse signal, in order to take into account the mismatch when ascertaining the error signal.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application

19/411,720Filed 8 Dec 2025

Priority

DE 10 2024 212 025.117 Dec 2024

Published

9 Jul 2026

Term ends

Not estimatedThe source records don’t support an estimate.

Classification14 codes

H03L 7/093
Concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal: using special…
H03L 7/1976
For fractional frequency division: using a phase accumulator for controlling the counter or frequency divider
H03L 7/00
Automatic control of frequency or phase
H03L 7/08
Using a reference signal applied to a frequency- or phase-locked loop: details of the phase-locked loop

Phase-Locked Loop with Synchronized Clock Signals

Life of this patent

Phase-Locked Loop with Synchronized Clock Signals

Life of this patent

Abstract

Claims11