US 2026/0197005 A1 · CRYSTAL-LESS TRANSCEIVER JITTER MITIGATION

Abstract

A system includes a crystal oscillator, a central switch transceiver coupled to the crystal oscillator, and a sensor transceiver. The central switch transceiver includes a transmitter circuit to employ a timing reference from the crystal oscillator to generate a self-clocking signal carrying first data and a clock and data recovery loop circuit to operate at a first bandwidth to sample second data received from the sensor transceiver. The sensor transceiver includes a reference clock recovery circuit to decode, from the self-clocking signal, a reference clock. A phase-locked loop (PLL) circuit generates a transmission clock, from the reference clock, operating at second bandwidth, for use in generating the second data. The first bandwidth is greater than or equal to a second bandwidth of the PLL circuit to mitigate jitter experienced by the clock and data recovery loop circuit due to jitter in the transmission clock.

Claims20

Dependent claims

A system comprising:

a crystal oscillator;
a central switch transceiver, coupled to the crystal oscillator, comprising:
a transmitter circuit to employ a timing reference from the crystal oscillator to generate a self-clocking signal carrying first data;
and
a clock and data recovery loop circuit to operate at a first bandwidth to sample second data received from a sensor transceiver;
and
the sensor transceiver comprising:
a reference clock recovery circuit to decode, from the self-clocking signal, a reference clock;
and
a phase-locked loop (PLL) circuit to generate a transmission clock, from the reference clock, for use in generating the second data, wherein the first bandwidth is greater than or equal to a second bandwidth of the PLL circuit to mitigate jitter experienced by the clock and data recovery loop circuit due to jitter in the transmission clock.

7 more elements

Dependencies are inferred from the claim text.

Crystal-less transceiver jitter mitigation

Life of this patent

Crystal-less transceiver jitter mitigation

Life of this patent

Abstract

Claims20