High voltage switch design in a low voltage process node with small quiescent current
AssigneeQUALCOMM Incorporated
InventorShamim AHMED
Life of this patent
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Abstract
A system-on-chip (SoC) is described. The SoC includes an interface physical input/output (IO) module (PHY) on a substrate. The interface PHY includes a high voltage power rail and a low voltage power rail. The SoC also includes a voltage regulator on the substrate and configured to supply to a low voltage to the low voltage power rail. The SoC further includes a high voltage switch on the substrate and coupled to the high voltage power rail of the interface PHY and the voltage regulator. The high voltage switch to maintain a quiescent current in the interface PHY below an activation current level.
Claims20
A system-on-chip (SoC) comprising:
- an interface physical input/output (IO) module (PHY) on a substrate, the interface PHY having a high voltage power rail and a low voltage power rail;
- a voltage regulator on the substrate and configured to supply to a low voltage to the low voltage power rail;
- and
- a high voltage switch on the substrate and coupled to the high voltage power rail of the interface PHY and the voltage regulator, the high voltage switch to maintain a quiescent current in the interface PHY below an activation current level.
A method to perform a power up sequence, the method comprising:
- receiving a master input voltage at an input of a high voltage switch coupled to a high voltage power rail of an input/output (IO) interface;
- supplying, by a voltage regulator, a low output voltage to a low voltage power rail of the IO interface;
- maintaining a quiescent current in the IO interface at a level below an activation current level when the master input voltage is applied to the high voltage switch;
- and
- directly supplying, using the high voltage switch, the master input voltage to the high voltage power rail of the IO interface to maintain the power up sequence of the IO interface.
Dependencies are inferred from the claim text.