Variable register threads with non-contiguous allocations
AssigneeIntel Corporation
InventorsAltug Koker, Supratim Pal, Naveen Matam, Vasanth Ranganathan
Life of this patent
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Abstract
Embodiments described herein provide techniques to enable an accelerator device to support a variable number of registers per-thread, where program code is associated with a register configuration selected from a plurality of register configurations, and the variable register configuration for a thread is configurable to make use of physically non-contiguous blocks of registers within a register file. The accelerator device includes circuitry to map physically non-contiguous blocks of registers into a virtual register space in which registers assigned to a thread appear contiguous to program code executed via the thread.
Claims20
A graphics processing unit comprising:
- a memory interface;
- a processing cluster coupled with the memory interface, the processing cluster including a plurality of graphics cores coupled via a data interconnect;
- and
- circuitry to dispatch workloads for execution by processing units within a graphics core of the plurality of graphics cores, the circuitry configured to:
- receive a request to dispatch program code for execution, the program code associated with a register configuration of a plurality of register configurations;
- select a processing unit of a plurality of processing units within the graphics core, the processing unit determined to have sufficient available resources to satisfy the register configuration associated with the program code;
- assign a plurality of virtual registers to a thread of the processing unit based on the register configuration associated with the program code;
- map a plurality of physical registers from a register file of the graphics core to the plurality of virtual registers assigned to the thread;
- and
- execute an instruction of the program code via the thread, the instruction having operations stored in one or more of the plurality of virtual registers.
A method comprising:
- receiving a request to dispatch program code for execution on a graphics processing unit, the program code associated with a register configuration of a plurality of register configurations;
- selecting a processing unit from a plurality of processing units, the processing unit determined to have sufficient available resources to satisfy the register configuration associated with the program code;
- assigning a plurality of virtual registers to a thread of the processing unit based on the register configuration associated with the program code;
- mapping a plurality of physical registers from a register file of the graphics processing unit to the plurality of virtual registers assigned to the thread;
- and
- executing an instruction of the program code via the thread, the instruction having operations stored in one or more of the plurality of virtual registers.
A graphics processing system comprising:
- a memory device;
- and
- a graphics processing unit coupled with the memory device, the graphics processing unit including a processing cluster including a plurality of graphics cores coupled via a data interconnect and circuitry to dispatch workloads for execution by processing units within a graphics core of the plurality of graphics cores, the circuitry configured to:
- receive a request to dispatch program code for execution, the program code associated with a register configuration of a plurality of register configurations;
- select a processing unit of a plurality of processing units within the graphics core, the processing unit determined to have sufficient available resources to satisfy the register configuration associated with the program code;
- assign a plurality of virtual registers to a thread of the processing unit based on the register configuration associated with the program code;
- map a plurality of physical registers from a register file of the graphics core to the plurality of virtual registers assigned to the thread;
- and
- execute an instruction of the program code via the thread, the instruction having operations stored in one or more of the plurality of virtual registers.
Dependencies are inferred from the claim text.