Processor, system and method providing a mechanism for accelerated ai interference
AssigneeIntel Corporation
InventorKiia Kaappoo Kallio
Life of this patent
Estimating the term…
Abstract
A processor comprises a memory to store numeric data in bit plane format and circuitry coupled to the memory to perform matrix operations on the stored data using adders. The bit plane format allows dynamic variations in bit sizes of values. A system includes a memory to store numeric data in bit plane format, a processor coupled to the memory, and a matrix multiplication module to perform matrix multiplication using adders. A method involves storing numeric data in bit plane format, retrieving the stored data, and performing matrix operations using adders. The processor, system, and method enable faster processing and reduced memory consumption compared to consecutive aligned bit sequences.
Claims18
An apparatus comprising:
- processing circuitry coupled to a memory, the processing circuitry to:
- store numeric data in bit plane format;
- and
- perform one or more matrix operations on the stored numeric data using a plurality of adders.
A method comprising:
- storing, by processing circuitry of a computing device, numeric data in bit plane format;
- and
- perform one or more matrix operations on the stored numeric data using a plurality of adders.
At least one computer-readable medium having stored thereon instructions which, when executed, cause a computing device to perform operations comprising:
- storing, by processing circuitry of the computing device, numeric data in bit plane format;
- and
- perform one or more matrix operations on the stored numeric data using a plurality of adders.
Dependencies are inferred from the claim text.