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AssigneeSemidynamics Technology Services, S.L.
InventorsROGER ESPASA SANS, PEDRO MARCUELLO PASCUAL, ALBERTO MORENO VEGA, JOSEP SANS I PRATS, SEBASTIANO POMATA
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Methods are provided of performing register-memory operations in a computer system including a processor with vector-registers, a memory, a cache with cache line-size and a bus with bus-width. These methods comprise: receiving a vector store instruction to transfer from vector-registers to memory a vector of elements, each element having an element length, ELEN; partitioning the vector store instruction into vector-region store instructions each defining a vector-region to be stored, each vector-region having a region length, RLEN, greater than the ELEN and a memory length, MLEN, equal to the cache line-size or the bus-width; buffering the vector-region store instructions so that each remains buffered until conditions enabling its execution are fulfilled; and performing, for each of the vector-region store instructions once released from the buffering, transfer from vector-registers to memory of the vector-region defined in/by the vector-region store instruction. Systems and computer programs suitable for performing said methods are also provided.
Method of performing or controlling register-memory operations in a computer system including a processor with a vector register file, a memory, a cache having a cache line size and a bus having a bus width, the method comprising:
System for performing or controlling register-memory operations in a computer system including a processor with a vector register file, a memory, a cache having a cache line size and a bus having a bus width, the system comprising:
Dependencies are inferred from the claim text.