Flexible systolic in-memory array testing device and control method thereof

A flexible systolic in-memory array testing device, comprising:

• a sub-board array composed of a plurality of sub-boards, wherein each of the sub-boards comprises a chip socket, a digital-to-analog conversion module, a driving module, a differential readout module, an analog-to-digital conversion module, a shift and accumulation module, and first to fourth bidirectional ports,
• the chip socket is configured to be placed with an in-memory array chip that performs a matrix operation with an input vector,
• bidirectional transmission of the input vector can be performed between the first bidirectional port and the second bidirectional port of a previous sub-board in a same row and between the first bidirectional port and the second bidirectional port of its own sub-board,
• the digital-to-analog conversion module is configured to obtain the input vector from the first bidirectional port and convert it into a voltage signal, and the driving module is configured to connect the voltage signal to the chip and provide a driving current;
• bidirectional transmission of a result vector can be performed between the third bidirectional port and the fourth bidirectional port of a foregoing sub-board in a same column and between the third bidirectional port and the shift and accumulation module of itself, and bidirectional transmission of the result vector can be performed between the fourth bidirectional port and the shift and accumulation module,
• the differential readout module comprises two inverting amplifier circuits and one adder-subtractor circuit, non-inverting input terminals of the two inverting amplifier circuits sample output currents of two adjacent columns in the chip, inverting input terminals are applied with clamping voltages, output terminals are connected to the adder-subtractor circuit for differential calculation and then perform outputting to the analog-to-digital conversion module for analog-to-digital conversion, and the shift and accumulation module is configured to perform shift accumulation on an analog-to-digital conversion result and a digital signal from the third bidirectional port or the fourth bidirectional port to achieve aggregation and obtain the result vector.