US 2026/0195133 A1 · Memory-Type Hierarchy for Instruction Patching

Abstract

This document describes techniques for updating instructions (e.g., code) in electronic devices. These techniques provide or otherwise support memory-type, hierarchy-based instruction-patching capabilities. Some examples presented herein provide memory arrangements that may be circuit-area friendly and/or operating-power friendly while also providing efficient patching and low latency. By way of example, techniques are provided that may be implemented in an apparatus having a first type of memory configured to store a set of instructions, with the set of instructions including an Nth instruction, and a second type of memory configured to store a patch set of instructions, with the patch set of instructions including a Yth patch instruction. The first type of memory is different from the second type of memory. The apparatus may include a module coupled to the first and second types of memory and configured to determine whether the Nth instruction is superseded by the Yth patch instruction.

Claims20

Dependent claims

An apparatus comprising:

a first type of memory configured to store a set of instructions, the set of instructions including an Nth instruction;
a second type of memory configured to store a patch set of instructions, the patch set of instructions including a Yth patch instruction, the second type of memory different from the first type of memory;
multiple memory locations;
and
a module coupled to the first type of memory, the second type of memory, and the multiple memory locations, the module configured to:
determine whether the Nth instruction is superseded by the Yth patch instruction based at least in part on a patched indicator stored in the multiple memory locations, the patched indicator associated with the Nth instruction and indicative of whether the Nth instruction is superseded, and
in response to a determination that the Nth instruction is superseded by the Yth patch instruction, specify the Yth patch instruction as a Kth instruction for execution, or
in response to a determination that the Nth instruction is not superseded by the Yth patch instruction, specify the Nth instruction as the Kth instruction for execution.

5 more elements

Dependencies are inferred from the claim text.

Memory-Type Hierarchy for Instruction Patching

Life of this patent

Memory-Type Hierarchy for Instruction Patching

Life of this patent

Abstract

Claims20