Vector simd vliw data path architecture

An electronic device comprising:

• a set of registers;
• and
• a functional unit configured to:
• receive a first operand from the set of registers, the first operand including a plurality of first data elements each having a first data size;
• receive a second operand from the set of registers, the second operand including a plurality of second data elements each having a second data size;
• receive a third operand from the set of registers, the third operand including a plurality of third data elements each having a third data size;
• perform a first plurality of operations on a first subset of the first data elements to produce a first set of results, wherein each operation of the first plurality of operations comprises:
• multiplying each first data element of the first subset of the first data elements by a respective second data element of a subset of the second data elements and a respective third data element of a subset of the third data elements to produce a set of products, wherein the subset of the second data elements and the subset of the third data elements is different for each operation;
• and
• summing the set of products to produce a respective result of the first set of results;
• perform a second plurality of operations on a second subset of the first data element to produce a second set of results, wherein each operation of the second plurality of operations comprises:
• multiplying each first data element of the second subset of the first data elements by a respective second data element of a subset of the second data elements and a respective third data element of a subset of the third data elements to produce a set of products, wherein the subset of the second data elements and the subset of the third data elements is different for each operation;
• and
• summing the set of products to produce a respective result of the second set of results;
• and
• output the first and second sets of results for storage in the set of registers.

A processing device comprising:

• a functional unit configured to, responsive to an instruction, produce an output value by:
• receiving a first operand having a plurality of first data elements representing first input data;
• receiving a second operand having a plurality of second data elements representing second input data;
• receiving a third operand representing a plurality of mask bits;
• and
• for each of a plurality of subsets of mask bits of the third operand, wherein each subset of mask bits does not overlap with any other subset of mask bits:
• performing a set of multiplication operations that multiplies the subset of mask bits, the first input data, and a respective subset of a plurality of subsets of second input data to produce a set of multiplication results;
• and
• summing the set of multiplication results to produce a respective sum value of a plurality of sum values;
• and
• outputting the plurality of sum values as the output value.