AVOIDING COMMANDED SYSTEM-ON-CHIP (SoC) SLEEP ENTRY FAILURE IN PROCESSOR-BASED DEVICES

A method for avoiding commanded System-on-Chip (SoC) sleep entry failure in processor-based devices, comprising:

• receiving, by a low-power mode (LPM) compliance logic circuit from each subsystem circuit of a plurality of subsystem circuits, a corresponding indication to start a corresponding No Acknowledgement (NACK) timer of a plurality of NACK timers of the LPM compliance logic circuit;
• generating, by the LPM compliance logic circuit, a plurality of NACK timer status indications corresponding to the plurality of NACK timers, wherein:
• each NACK timer status indication is set to a first value if the corresponding NACK timer is cancelled by the corresponding subsystem circuit upon entry into an LPM;
• and
• each NACK timer status indication is set to a second value if the corresponding NACK timer expires without being cancelled;
• receiving, by the LPM compliance logic circuit from an Electrically Isolated Island (EII) / Safety Island (SAIL) circuit, an enable indication;
• and
• responsive to receiving the enable indication:
• generating, by the LPM compliance logic circuit, an LPM compliance status indication in response to the plurality of NACK timer status indications and the enable indication;
• and
• transmitting, by the LPM compliance logic circuit, the LPM compliance status indication to the EII/SAIL circuit.

A non-transitory computer-readable medium, having stored thereon computer-executable instructions that, when executed by a processor device of a processor-based device, cause the processor device to:

• receive, from each subsystem circuit of a plurality of subsystem circuits, a corresponding indication to start a corresponding No Acknowledgement (NACK) timer of a plurality of NACK timers;
• generate a plurality of NACK timer status indications corresponding to the plurality of NACK timers, wherein:
• each NACK timer status indication is set to a first value if the corresponding NACK timer is cancelled by the corresponding subsystem circuit upon entry into a low-power mode (LPM);
• and
• each NACK timer status indication is set to a second value if the corresponding NACK timer expires without being cancelled;
• receive an enable indication from an Electrically Isolated Island (EII) / Safety Island (SAIL) circuit;
• and
• responsive to receiving the enable indication:
• generate an LPM compliance status indication in response to the plurality of NACK timer status indications and the enable indication;
• and
• transmit the LPM compliance status indication to the EII/SAIL circuit.