Distributed voltage regulating circuit, method of operating distributed voltage regulating circuit, and system-on-chip including distributed voltage regulating circuit

An operating method of a distributed voltage regulating circuit comprising a main voltage regulator and an auxiliary voltage regulator, the operating method comprising:

• comparing, by the main voltage regulator, a feedback voltage of an output node with a reference voltage to generate an error voltage;
• controlling, by the main voltage regulator, a first power transistor based on the error voltage to provide a first current to the output node;
• generating, by the main voltage regulator, a first control signal based on the error voltage;
• generating, by the main voltage regulator, a second control signal based on a current difference between a first sampling current of the first power transistor and a second sampling current of a second power transistor in the auxiliary voltage regulator;
• providing, by the main voltage regulator, the first control signal and the second control signal to the auxiliary voltage regulator;
• and
• controlling, by the auxiliary voltage regulator, the second power transistor based on a differential amplification signal for the first control signal and the second control signal to provide a second current to the output node.

A system-on-chip comprising:

• a main voltage regulator comprising a first power transistor configured to provide a first current to an output node based on a feedback voltage and a reference voltage;
• an auxiliary voltage regulator comprising a second power transistor configured to provide a second current to the output node based on a first control signal and a second control signal;
• and
• at least one load circuit configured to operate based on a voltage of the output node,
• wherein the main voltage regulator is configured to generate the first control signal based on the feedback voltage and the reference voltage and generate the second control signal based on a first sampling current of the first power transistor and a second sampling current of the second power transistor.