Semiconductor package

A semiconductor package comprising:

• a package substrate;
• a semiconductor chip on an upper surface of the package substrate;
• a mold layer covering the semiconductor chip;
• and
• external connection terminals disposed on a lower surface of the package substrate,
• wherein the package substrate includes:
• a core layer;
• lower wirings and a dummy wiring on a lower surface of the core layer;
• a solder resist layer covering the lower wirings and the dummy wiring;
• an insulating structure penetrating the solder resist layer and covering side surfaces of the lower wirings and a side surface of the dummy wiring;
• and
• a first metal pattern on a lower surface of the dummy wiring,
• wherein the solder resist layer includes first openings exposing a portion of lower surfaces of the lower wirings and a second opening exposing a portion of the lower surface of the dummy wiring,
• wherein the external connection terminals are respectively disposed on the lower surfaces of the lower wirings exposed by the first openings,
• wherein the first metal pattern is disposed in the second opening,
• wherein the insulating structure includes an insulating material different from that of the solder resist layer,
• wherein the lower wirings and the dummy wiring include a first metal, and
• wherein the first metal pattern includes a second metal different from the first metal.

A semiconductor package comprising:

• a package substrate;
• a first semiconductor chip and a second semiconductor chip on an upper surface of the package substrate and horizontally spaced from each other;
• a mold layer covering the first semiconductor chip and the second semiconductor chip;
• and
• external connection terminals on a lower surface of the package substrate,
• wherein the package substrate includes:
• a core layer;
• lower wirings on a lower surface of the core layer;
• a solder resist layer covering the lower wirings;
• and
• an insulating structure in direct contact with side surfaces of the lower wirings,
• wherein the insulating structure includes at least one of an epoxy-based polymer, a polyimide-based polymer, a silicon-based polymer, and a polybenzoxazole (PBO)-based polymer,
• wherein a horizontal width of the insulating structure decreases from a lower surface to an upper surface of the insulating structure, and
• wherein a level of the lower surface of the insulating structure is equal to or higher than a level of the lower surface of the solder resist layer and equal to or lower than a level of a lower surface of each of the lower wirings.