US 2026/0191009 A1 · SEMICONDUCTOR PACKAGE

Abstract

Example embodiments are directed to a semiconductor package having a relatively reduced thickness and configured to reduce signal crosstalk between two channels used by the semiconductor package. The semiconductor package includes a package substrate including a first substrate pad and a second substrate pad, at least one first semiconductor chip including first chip pads and on the package substrate, at least one second semiconductor chip including second chip pads and on the first semiconductor chip, a first printed wiring connecting some of the second chip pads and the first chip pads to the first substrate pad, a second printed wiring connecting the other second chip pads to the second substrate pad, an isolation insulating layer insulating the first printed wiring from the second printed wiring in an overlapping region, in which the first printed wiring and the second printed wiring overlap, and a ground layer inside the isolation insulating layer.

Claims20

Dependent claims

A semiconductor package comprising:

a package substrate including a first substrate pad and a second substrate pad;
at least one first semiconductor chip including a plurality of first chip pads and on the package substrate in a stepped structure;
at least one second semiconductor chip including a plurality of second chip pads and on the at least one first semiconductor chip in a stepped structure;
a first printed wiring connecting a portion of the plurality of second chip pads and the plurality of first chip pads to the first substrate pad;
a second printed wiring connecting a remaining portion of the plurality of second chip pads to the second substrate pad;
an isolation insulating layer isolating the first printed wiring from the second printed wiring and covering a portion of the first printed wiring on the at least one first semiconductor chip in an overlapping region in which the first printed wiring overlaps the second printed wiring;
and
a ground layer inside the isolation insulating layer.

5 more elements

A semiconductor package comprising:

a package substrate including a first substrate pad and a second substrate pad;
at least one first semiconductor chip including a first signal chip pad and on the package substrate in a stepped structure;
at least one second semiconductor chip including a second signal chip pad and on the at least one first semiconductor chip in a stepped structure;
a first printed wiring connecting the first signal chip pad to the first substrate pad;
a second printed wiring connecting the second signal chip pad to the second substrate pad;
a lower isolation insulating layer covering the first printed wiring in an overlapping region in which the first printed wiring overlaps the second printed wiring;
a ground layer covering the lower isolation insulating layer;
and
an upper isolation insulating layer covering the ground layer and having a portion of the second printed wiring on a top surface of the upper isolation insulating layer.

6 more elements

Dependencies are inferred from the claim text.

Semiconductor package

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Semiconductor package

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Abstract

Claims20