Semiconductor device

A semiconductor device comprising:

• a substrate including a PMOSFET region;
• an active pattern on the PMOSFET region;
• a channel pattern being on the active pattern, the channel pattern including a plurality of semiconductor patterns vertically spaced apart from each other;
• a source/drain pattern connected to the plurality of semiconductor patterns;
• a gate electrode being on the plurality of semiconductor patterns, the gate electrode including an inner electrode interposed between a pair of semiconductor patterns that are adjacent to each other, among the plurality of semiconductor patterns, an outer electrode on an uppermost semiconductor pattern among the plurality of semiconductor patterns;
• a gate insulating layer between the gate electrode and the semiconductor patterns adjacent to each other;
• and
• an inner spacer interposed between the source/drain pattern and the gate insulating layer surrounding the inner electrode,
• wherein the source/drain pattern includes a first semiconductor layer in contact with each of the plurality of semiconductor patterns,
• the inner spacer has a first horizontal width in a first direction,
• the first semiconductor layer has a second horizontal width in the first direction, and
• the second horizontal width is different from the first horizontal width.

A semiconductor device comprising:

• a first active pattern on a first active region of a substrate and a second active pattern on a second active region of the substrate;
• an element separation layer configured to fill a trench defining the first and second active patterns;
• a first channel pattern on the first active pattern and a second channel pattern on the second active pattern, each of the first and second channel patterns including a first semiconductor pattern, a second semiconductor pattern and a third semiconductor pattern vertically spaced apart from each other;
• a first source/drain pattern connected to the first channel pattern and a second source/drain pattern connected to the second channel pattern;
• a gate electrode on the first to third semiconductor patterns;
• a gate insulating layer between the first to third semiconductor patterns and the gate electrode;
• a first inner spacer interposed between the gate insulating layer and the first source/drain pattern, and a second inner spacer interposed between the gate insulating layer and the second source/drain pattern;
• a gate spacer on a sidewall of the gate electrode;
• a gate capping pattern on an upper surface of the gate electrode;
• an interlayered insulating layer on the gate capping pattern;
• an active contact penetrating the interlayered insulating layer to be electrically connected to each of the first source/drain pattern and the second source/drain pattern;
• a metal-semiconductor compound layer interposed between the active contact and the first source/drain pattern, and between the active contact and the second source/drain pattern;
• a gate contact penetrating the interlayered insulating layer and the gate capping pattern to be electrically connected to the gate electrode;
• a first metal layer being on the interlayered insulating layer, the first metal layer including power wires, the power wires electrically connected to the active contact and the gate contact;
• and
• a second metal layer on the first metal layer,
• wherein the second metal layer includes second wires electrically connected to the first metal layer,
• the second active region is a PMOSFET region,
• the second source/drain pattern includes a first semiconductor layer in contact with the first to third semiconductor patterns, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer,
• the second inner spacer has a silicon nitride-based insulating material, and
• the second source/drain pattern is spaced apart from the gate electrode by the second inner spacer.