US 2026/0190470 A1 · SOURCE/DRAIN REGIONS IN STACKING TRANSISTORS AND METHODS OF FORMING THE SAME

Abstract

In an embodiment, a method includes forming an upper gate structure adjacent to a first source/drain region and a second source/drain region and a lower gate structure adjacent to a third source/drain region; patterning a first opening and a second opening through a first dielectric layer to expose the first source/drain region and the second source/drain region; patterning to extend the second opening through a second dielectric layer to expose the third source/drain region; forming a protective layer over exposed surfaces of the first dielectric layer; forming a first epitaxial regrowth layer over the first source/drain region and a second epitaxial regrowth layer over the second source/drain region; removing the protective layer; forming a first source/drain contact to the first epitaxial regrowth layer; and forming a second source/drain contact to the second epitaxial regrowth layer and the third source/drain region.

Claims20

Dependent claims

A method comprising:

forming an upper gate structure adjacent to a first source/drain region and a second source/drain region and a lower gate structure adjacent to a third source/drain region;
patterning a first opening and a second opening through a first dielectric layer to expose the first source/drain region and the second source/drain region;
patterning to extend the second opening through a second dielectric layer to expose the third source/drain region;
forming a protective layer over exposed surfaces of the first dielectric layer;
forming a first epitaxial regrowth layer over the first source/drain region and a second epitaxial regrowth layer over the second source/drain region;
removing the protective layer;
forming a first source/drain contact to the first epitaxial regrowth layer;
and
forming a second source/drain contact to the second epitaxial regrowth layer and the third source/drain region.

6 more elements

A semiconductor device comprising:

a first epitaxial region, the first epitaxial region comprising a first epitaxial material;
a first silicide region on the first epitaxial region;
first nanostructures adjacent to the first epitaxial region;
a second epitaxial region overlapping the first epitaxial region, the second epitaxial region comprising a second epitaxial material being different from the first epitaxial material;
a second silicide region on the second epitaxial region;
an interlayer dielectric layer disposed over the first epitaxial region and below the second epitaxial region;
a contact plug extending through the second epitaxial region and the interlayer dielectric layer to electrically couple to the first epitaxial region, wherein an electrical conductivity of the contact plug is greater than an electrical conductivity of the first epitaxial region;
a third epitaxial region laterally adjacent to the second epitaxial region, the third epitaxial region comprising the second epitaxial material and a third epitaxial material, the third epitaxial material being different from the first epitaxial material and the second epitaxial material;
a third silicide region on the third epitaxial region, the third silicide region being in contact with the third epitaxial material of the third epitaxial region;
second nanostructures extending from the second epitaxial region to the third epitaxial region;
a first gate structure around the first nanostructures;
and
a second gate structure overlapping the first gate structure and around the second nanostructures.

10 more elements

Dependencies are inferred from the claim text.

Source/drain regions in stacking transistors and methods of forming the same

Life of this patent

Source/drain regions in stacking transistors and methods of forming the same

Life of this patent

Abstract

Claims20