Multi-threshold gate dielectric patterning scheme using individualized gate tubs

An apparatus, comprising:

• a first nanoribbon stack in a first transistor structure, a first dielectric stack on first nanoribbons in the first nanoribbon stack, a first gate electrode on the first dielectric stack;
• a second nanoribbon stack in a second transistor structure, a second dielectric stack on second nanoribbons in the second nanoribbon stack, a second gate electrode on the second dielectric stack, the second dielectric stack comprising a second thickness different than a first thickness of the first dielectric stack;
• and
• a dielectric structure separating the first and second gate electrodes, wherein a width of the dielectric structure is less than half of a height of the first nanoribbon stack.

A method, comprising:

• forming an isolation structure through a dummy gate and between a first stack of first nanoribbons and a second stack of second nanoribbons, the isolation structure comprising opposing first and second sides;
• opening a first cavity on the first side of the isolation structure and over the first stack;
• forming a first dielectric stack on the first nanoribbons;
• opening a second cavity on the second side of the isolation structure and over the second stack;
• forming a second dielectric stack on the second nanoribbons;
• and
• forming a first gate electrode over the first stack and a second gate electrode over the second stack, the first and second gate electrodes separated by the isolation structure.