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US 2026/0190448 A1Published application
Raised source/drain transistor
OwnerManoj Mehrotrainventor
Life of this patent
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Abstract
Transistors with raised source/drain structures and methods of making the transistors are described. A method for making such transistors includes forming a first gate and a second gate on a substrate, forming a p-doped region adjacent the first gate, and forming an n-doped region adjacent the second gate. The method further includes forming a silicon germanium (SiGe) region in a portion of the p-doped region. Subsequently, the method simultaneously forms raised source-drain structures over the SiGe region and on the n-doped region.
Claims20
A semiconductor device, comprising:
- a p-channel field effect transistor (pFET) including a gate structure over a surface of a substrate, a spacer on a sidewall of the gate structure, and a raised drain next to the spacer, the raised drain having at least a portion of a silicon germanium (SiGe) structure and a silicon structure disposed on the SiGe structure.
A semiconductor device, comprising:
- a p-channel field effect transistor (pFET) including a first gate structure over a surface of a substrate and a first raised drain next to the first gate structure, the first raised drain having at least a portion of a silicon germanium (SiGe) structure and a first silicon structure disposed on the SiGe structure;
- and
- an n-channel field effect transistor (nFET) including a second gate structure over the surface of the substrate and a second raised drain next to the second gate structure, the second raised drain having a second silicon structure disposed on the substrate, wherein the first silicon structure of the pFET has a first thickness and the second silicon structure of the nFET has a second thickness, the second thickness less than the first thickness.
Dependencies are inferred from the claim text.