US 2026/0190446 A1 · SELECTIVE NANOWIRE RELEASE AND BACKFILL FOR TRANSISTOR CHANNEL STRESS ENGINEERING IN NANOWIRE FIELD EFFECT TRANSISTORS

Abstract

Devices, integrated circuit transistor structures, systems, and techniques are described herein related to gate all around field effect transistor circuits having an n-type transistor integrated with a p-type transistor such that each has stress engineering in the channel material thereof. The nanowires of the p-type transistor are released and surrounded by a sacrificial flowable oxide structure during source and drain material growth to apply compressive stress to the channel material. The n-type transistor source and drain are grown in the presence of a sacrificial lattice matched material to apply tensile stress to the channel material, and the nanowires are subsequently released. After removal of the sacrificial flowable oxide structure, gate structures are coupled to the n-type and p-type transistors.

Claims20

Dependent claims

An apparatus, comprising:

an n-type transistor comprising a plurality of first semiconductor structures extending between a first source structure and a first drain structure, a first gate structure coupled to the first semiconductor structures, and a first spacer structure on and between the first gate structure and the first source structure or the first drain structure, the first spacer structure comprising a first dielectric material and germanium;
and
a p-type transistor comprising a plurality of second semiconductor structures extending between a second source structure and a second drain structure, a second gate structure coupled to the second semiconductor structures, and a second spacer structure between the second gate structure and the second source structure or the second drain structure, the second spacer structure comprising the first dielectric material or a second dielectric material, and absent germanium.

Dependencies are inferred from the claim text.

Selective nanowire release and backfill for transistor channel stress engineering in nanowire field effect transistors

Life of this patent

Selective nanowire release and backfill for transistor channel stress engineering in nanowire field effect transistors

Life of this patent

Abstract

Claims20