Semiconductor device

A semiconductor device comprising:

• a substrate comprising a cell region and a peripheral region located outside the cell region;
• a first conductivity type semiconductor layer on an upper surface of the substrate,
• a second conductivity type doped well region within the first conductivity type semiconductor layer;
• a gate electrode on the first conductivity type semiconductor layer;
• a gate insulation layer between the first conductivity type semiconductor layer and the gate electrode;
• a source electrode on the second conductivity type doped well region;
• and
• a drain electrode under a lower surface of the substrate,
• wherein the source electrode comprises
• a first source electrode on the gate electrode,
• a plurality of second source electrodes above the first source electrode, and
• a plurality of interlayer source electrodes, each of the plurality of interlayer source electrodes comprising (i) a plurality of insulation structures spaced apart from one another in a first direction parallel to the upper surface of the substrate and (ii) a plurality of conductive lines between adjacent insulation structures of the plurality of insulation structures, and disposed between the first source electrode and adjacent second source electrode of the plurality of second source electrodes, and
• wherein the plurality of the second source electrodes and the plurality of interlayer source electrodes are alternately stacked in a third direction.

A semiconductor device, comprising:

• a substrate comprising a cell region and a peripheral region located outside the cell region;
• a first conductivity type semiconductor layer on an upper surface of the substrate;
• a second conductivity type doped well region within the first conductivity type semiconductor layer;
• a gate electrode on the first conductivity type semiconductor layer;
• a gate insulation layer between the first conductivity type semiconductor layer and the gate electrode;
• a source electrode on the second conductivity type doped well region;
• and
• a drain electrode below a lower surface of the substrate,
• wherein the source electrode comprises
• a first source electrode on the gate electrode,
• a 1st interlayer source electrode on the first source electrode and comprising (i) a plurality of insulation structures spaced apart from one another in a first direction that is parallel to the upper surface of the substrate and (ii) a plurality of conductive lines disposed between the insulation structures,
• a 1st second source electrode on the 1st interlayer source electrode,
• a 2nd interlayer source electrode on the 1st second source electrode and comprising (i) a plurality of insulation structures spaced apart from one another in the first direction and (ii) a plurality of conductive lines between the plurality of insulation structures,
• a 2nd second source electrode on the 2nd interlayer source electrode, and
• wherein each of center points of the plurality of insulation structures of the 1st interlayer source electrode along the first direction and a second direction that is parallel to the upper surface of the substrate and different from the first direction, does not overlap with, in a third direction, each of center points of the plurality of insulation structures of the 2nd interlayer source electrode along the first direction and the second direction, the third direction being perpendicular to the upper surface of the substrate.